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* svga: add the has_backed_views flagCharmaine Lee2017-04-073-0/+15
| | | | | | | | | The new has_backed_views flag specifies if any of the render target views or depth stencil view is a backing surface view. The flag is used in svga_propagate_rendertargets() so it can return early if there is no surface to propagate. Reviewed-by: Brian Paul <[email protected]>
* svga: only destroy render target view from a context that created itCharmaine Lee2017-04-071-12/+23
| | | | | | | | | | | | | | A texture can be destroyed from a different context from which it is created, but destroying the render target view from a different context will cause svga device errors. Similar to shader resource view, this patch skips destroying render target view or depth stencil view from a non-parent context. Fixes driver errors running NobelClinician Viewer application. Tested with NobelClinician Viewer, MTT piglit, glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: disable rasterization if rasterizer_discard is set or FS undefinedCharmaine Lee2017-04-076-39/+128
| | | | | | | | | | | | | | | | | | | With this patch, rasterization will be disabled if the rasterizer_discard flag is set or the fragment shader is undefined due to missing position output from the vertex/geometry shader. Tested with piglit test glsl-1.50-geometry-primitive-id-restart. Also tested with full MTT glretrace and piglit. v2: As suggested by Roland, to properly disable rasterization, besides setting FS to NULL, we will also need to disable depth and stencil test. v3: As suggested by Brian, set SVGA_NEW_DEPTH_STENCIL_ALPHA dirty bit in svga_bind_rasterizer_state() if the rasterizer_discard flag is changed. Reviewed-by: Brian Paul <[email protected]>
* svga: do not emulate wide points in GS when doing transform feedbackCharmaine Lee2017-04-071-3/+5
| | | | | | | | | | Emulating wide points in geometry shader when doing transform feedback is problematic. This patch disables the emulation. Tested with piglit test ext_transform_feedback-points. Also tested with MTT glretrace, mesa demos pointblast and spriteblast. Reviewed-by: Brian Paul <[email protected]>
* gallium/util: tweak backtrace format with libunwindRob Clark2017-04-071-10/+16
| | | | | | | To work with addr2line.sh we also need the relative offset within the DSO. And addr2line.sh gets confused by the leading stackframe number. Signed-off-by: Rob Clark <[email protected]>
* gallium/util: cache symbol lookup with libunwindRob Clark2017-04-072-27/+94
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/util: fix missing limit check in libunwind backtraceRob Clark2017-04-071-1/+1
| | | | | Fixes: 70c272004f ("gallium/util: libunwind support") Signed-off-by: Rob Clark <[email protected]>
* gallium/radeon: fix typo in radeon_winsys.hSamuel Pitoiset2017-04-071-1/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* swr: [rasterizer core] SIMD16 Frontend WIPTim Rowley2017-04-054-75/+1299
| | | | | | Implement widened binner for SIMD16 Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Enable 8x2 backendTim Rowley2017-04-051-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer codegen] remove copy of makoTim Rowley2017-04-0518-7201/+0
| | | | | | | | mako is already a mesa build requirement, extra copy not needed. Tested building against mesa build baseline (mako-0.8.0). Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core/memory] Move intrinics to _simd functionsTim Rowley2017-04-055-117/+112
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Programmable sample position supportTim Rowley2017-04-0512-596/+267
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [configure.ac/scons] require c++14Tim Rowley2017-04-052-3/+3
| | | | | | New C++ features used by upcoming swr changes. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Fix center sample patternTim Rowley2017-04-053-26/+26
| | | | | | Fix long hidden bug in rasterizer handling of center sample pattern. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core/memory] Fix missing avx512 storetileTim Rowley2017-04-053-23/+14
| | | | | | | Fix pre-processor macro handing to eliminate silently missing implementation for AVX512. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] SIMD16 Frontend WIPTim Rowley2017-04-052-37/+14
| | | | | | Implement widened VS output for SIMD16 Reviewed-by: Bruce Cherniak <[email protected]>
* Revert "etnaviv: Cannot render to rb-swapped formats"Christian Gmeiner2017-04-051-5/+2
| | | | | | | | | This reverts commit 658568941d5e232d690e1ffbcddbd6ea9685693a. With the help of shader variants we can render to rb-swapped formats now. Fixes about 60 piglits. Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: add support for rb swapChristian Gmeiner2017-04-054-0/+38
| | | | | | | If we render to rb swapped format we will create a shader variant doing the involved swizzing in the pixel shader. Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: adapt shader-db output for variant supportChristian Gmeiner2017-04-051-15/+15
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: bring back shader-db tracesChristian Gmeiner2017-04-051-0/+9
| | | | | | | | | If shader-db run, create a standard variant immediately (as otherwise nothing will trigger the shader to be actually compiled). Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: add etna_shader_key and generate variants if neededChristian Gmeiner2017-04-058-29/+97
| | | | Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: pass a preallocated variant to compilerChristian Gmeiner2017-04-054-38/+62
| | | | | | | | | | | In the long run the compiler needs to know the specifc variant 'key' in order to compile appropriate assembly. With this commit the variant knows its shader and we are able pass the preallocated variant into etna_compile_shader(..). This saves us from passing extra ptrs everywhere. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: make specs constChristian Gmeiner2017-04-051-1/+1
| | | | Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: add struct etna_shader_stateChristian Gmeiner2017-04-055-23/+24
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: add basic shader variant supportChristian Gmeiner2017-04-053-4/+60
| | | | | | | | | This commit adds some basic infrastructure to handle shader variants. We are still creating exactly one shader variant for each shader. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: s/etna_shader/etna_shader_variantChristian Gmeiner2017-04-057-34/+34
| | | | | | Prep work to add shader variant support. Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: remove not needed forward declarationsChristian Gmeiner2017-04-051-2/+0
| | | | Signed-off-by: Christian Gmeiner <[email protected]>
* gallium/util: honour LIBUNWIND_CFLAGSEmil Velikov2017-04-051-0/+1
| | | | | Fixes: 70c272004f72 ("gallium/util: libunwind support") Signed-off-by: Emil Velikov <[email protected]>
* st/clover: Fix build after shrink of pipe_boxAaron Watry2017-04-051-3/+3
| | | | | | | | Fixes: 3dfe61e ("gallium: decrease the size of pipe_box - 24 -> 16 bytes") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100569 Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Tested-by: Vinson Lee <[email protected]>
* radeonsi: enable ARB_shader_ballotNicolai Hähnle2017-04-051-1/+3
| | | | | | | | Require LLVM 5.0 or later because LLVM 4.0 is easily fooled into putting the lane select of llvm.amdgcn.readlane into a VGPR and then fails to continue to compile. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: optimization barriers to work around LLVM deficienciesNicolai Hähnle2017-04-051-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Notably, llvm.amdgcn.readfirstlane and llvm.amdgcn.icmp may be hoisted out of loops or if/else branches in cases like if (cond) { v = readFirstInvocationARB(x); ... use v ... } else { v = readFirstInvocationARB(x); ... use v ... } ===> v = readFirstInvocationARB(x); if (cond) { ... use v ... } else { ... use v ... } The optimization barrier is a heavy hammer to stop that until LLVM is taught the semantics of the intrinsic properly. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: strengthen emit_optimization_barrierNicolai Hähnle2017-04-052-4/+38
| | | | | | | | | | | | | LLVM will lift inline assembly out of if-else-blocks if both paths have the same inline assembly. Prevent this by adding an irrelevant unique text to the assembly. This requires the LLVM assembly parser to be initialized. Furthermore, allow forcing subsequent computations to happen after the optimization barrier by defining a data dependency. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit TGSI_OPCODE_READ_*Nicolai Hähnle2017-04-051-0/+38
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit TGSI_OPCODE_BALLOTNicolai Hähnle2017-04-051-0/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement TGSI_SEMANTIC_SUBGROUP_*Nicolai Hähnle2017-04-051-0/+40
| | | | | | 64-bit system values are stored as v2i32 to simplify the fetch logic. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: support 64-bit system valuesNicolai Hähnle2017-04-051-4/+20
| | | | | | | For simplicitly, always store system values as 32-bit values or arrays of 32-bit values. 64-bit values are unpacked and packed accordingly. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: bump RADEON_LLVM_MAX_SYSTEM_VALUESNicolai Hähnle2017-04-052-1/+3
| | | | | | | ARB_shader_ballot introduces 7 new system values that can be used in all shader stages. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add SUBGROUP_* semanticsIlia Mirkin2017-04-053-0/+65
| | | | | | | | v2: add documentation (Nicolai) Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add BALLOT/READ_* opcodesIlia Mirkin2017-04-053-17/+63
| | | | | | | | | | | | | | | | | | | | v2 (Nicolai): - BALLOT isn't per-channel - expand the documentation (also for VOTE_*) v3: - only BALLOT returns a 64-bit lanemask (Boyan) - relax the requirement on READ_INVOC: the invocation number to read from must be uniform within a sub-group. This matches the GL_ARB_shader_ballot spect (and the v_readlane instruction of AMD GCN) v4: - hopefully really fix the doc of VOTE_* returns (Ilia) Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2)
* gallium: add PIPE_CAP_TGSI_BALLOTNicolai Hähnle2017-04-0517-0/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* swr: automake: add gen_common.py to the tarballEmil Velikov2017-04-051-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: enable ARB_sparse_bufferNicolai Hähnle2017-04-051-1/+10
| | | | | | | | v2: - fill in DRM version requirement - disable on SI due to CP DMA faults Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: disable SDMA clears and copies for sparse buffersNicolai Hähnle2017-04-053-4/+11
| | | | | | | | | VM faults cannot be disabled for SDMA on <= VI. We could still use SDMA by asking the winsys about which parts of the buffers are committed. This is left as a potential future improvement. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: implement pipe->resource_commitNicolai Hähnle2017-04-051-0/+35
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: transfers and invalidation for sparse buffersNicolai Hähnle2017-04-051-10/+24
| | | | | | Sparse buffers can never be mapped by the CPU. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: implement sparse buffer creationNicolai Hähnle2017-04-051-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: sparse buffer debugging helpersNicolai Hähnle2017-04-051-0/+61
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: take fences when freeing a backing bufferNicolai Hähnle2017-04-051-3/+11
| | | | | | | | | | | We never add fences to backing buffers during submit. When we free a backing buffer, it must inherit the sparse buffer's fences, so that it doesn't get re-used prematurely via the cache. v2: - remove pipe_mutex_* Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add sparse buffers to CSNicolai Hähnle2017-04-052-16/+140
| | | | | | | | | | ... and implement the corresponding fence handling. v2: - add missing bit in amdgpu_bo_is_referenced_by_cs_with_usage - remove pipe_mutex_* Reviewed-by: Marek Olšák <[email protected]>
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