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* Gallivm: fix the constant layout, this gets a bunch of progs/ working. ↵Stephane Marchesin2008-10-076-21/+78
| | | | Notably, gears doesn't.
* CELL: changes to generate SPU code for stencilingRobert Ellison2008-10-0312-146/+1091
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This set of code changes are for stencil code generation support. Both one-sided and two-sided stenciling are supported. In addition to the raw code generation changes, these changes had to be made elsewhere in the system: - Added new "register set" feature to the SPE assembly generation. A "register set" is a way to allocate multiple registers and free them all at the same time, delegating register allocation management to the spe_function unit. It's quite useful in complex register allocation schemes (like stenciling). - Added and improved SPE macro calculations. These are operations between registers and unsigned integer immediates. In many cases, the calculation can be performed with a single instruction; the macros will generate the single instruction if possible, or generate a register load and register-to-register operation if not. These macro functions are: spe_load_uint() (which has new ways to load a value in a single instruction), spe_and_uint(), spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint(). - Added facing to fragment generation. While rendering, the rasterizer needs to be able to determine front- and back-facing fragments, in order to correctly apply two-sided stencil. That requires these changes: - Added front_winding field to the cell_command_render block, so that the state tracker could communicate to the rasterizer what it considered to be the front-facing direction. - Added fragment facing as an input to the fragment function. - Calculated facing is passed during emit_quad().
* draw: modify prefetching slightlyKeith Whitwell2008-10-021-4/+15
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* draw: don't keep refetching constant inputsKeith Whitwell2008-10-026-62/+144
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* rtasm: add prefetch instructionsKeith Whitwell2008-10-022-0/+31
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* draw: add streamlined paths for fetching linear vertsKeith Whitwell2008-10-023-66/+134
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* Gallivm: add slt. glxgears should be running, except it isn't.Stephane Marchesin2008-10-024-66/+101
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* Gallivm: port to llvm 2.4.Stephane Marchesin2008-10-025-149/+149
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* Gallivm: fix off-by-one.Stephane Marchesin2008-10-021-1/+1
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* Gallivm: more instructions.Stephane Marchesin2008-10-023-8/+73
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* Gallivm: make it compile again, add some opcodes.Stephane Marchesin2008-10-025-485/+771
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* util: No-op u_sse.h outside PIPE_ARCH_X86/X86_64.José Fonseca2008-10-011-1/+6
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* tgsi: Include p_config.h.José Fonseca2008-10-011-0/+2
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* cell: Moved X86 checks to wrap #include section so that Cell targets will ↵Jonathan White2008-09-301-2/+2
| | | | compile again.
* util: Fix util_fast_pow/exp2/log2.José Fonseca2008-10-012-69/+64
| | | | | | | | | | | - Use a lookup table for log2. - Compute (float) (1 << ipart) by tweaking with the exponent directly to avoid integer overflow and float conversion. - Also table negative exponents to avoid float division and branching. - Implement util_fast_exp as function of util_fast_exp2.
* tgsi: SSE2 optimized exp2, log2 and pow implementations.José Fonseca2008-09-301-76/+211
| | | | | | | | | | | | Special care must be taken when calling compiler generated SSE2 functions from the runtime generated SSE2: saving the xmm registers, and notify gcc the stack is not 16byte aligned. It would be more efficient to keep the stack pointer 16byte aligned, but too hairy, and not consistent in all x86 architectures. This has been tested in linux x86 and windows x86 userspace. Not tested on x86-64 because it is broken for other reasons (even without this change).
* util: Header for SSE2 intrinsics portability.José Fonseca2008-09-301-0/+72
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* rtasm: Implement immediate group 1 instructions. Fix SIB emition.José Fonseca2008-09-292-15/+62
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* cell: checkpoint: more work in emit_function_call()Brian Paul2008-09-261-6/+39
| | | | Simple function call works now, but we don't save/restore the caller's registers yet.
* cell: stub-out sin/cos function bodies to avoid trashing caller's stack for nowBrian Paul2008-09-261-0/+10
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* gallium: SPU register commentsBrian Paul2008-09-261-2/+2
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* cell: move command processing code into new spu_command.c fileBrian Paul2008-09-264-556/+611
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* cell: move debug-related declarationsBrian Paul2008-09-262-2/+8
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* cell: move debug macros into new spu_debug.hBrian Paul2008-09-262-27/+63
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* cell: move really_clear_tiles()Brian Paul2008-09-263-40/+41
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* cell: align instruction buffers to 8-byte, not 32-byte boundaryBrian Paul2008-09-263-8/+8
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* cell: asst clean-up, var renamingBrian Paul2008-09-261-10/+9
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* cell: remove unneeded blend/depth_stencil subclassesBrian Paul2008-09-264-72/+15
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* cell: checkpoint: support for function calls in SPU shadersBrian Paul2008-09-268-3/+254
| | | | | | | Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to know the address of some functions in the SPU address space. Send that info to the PPU/main memory rather than patch up shaders on the SPU side. Not finished/tested yet...
* cell: inst reorder to save a cycleBrian Paul2008-09-261-1/+1
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* st: change from ** to * for st_unreference_framebuffer()Alan Hourihane2008-09-263-3/+3
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* util: Update fast_log2 article url.José Fonseca2008-09-261-1/+1
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* add cso_hash_contains() functionAlan Hourihane2008-09-242-0/+12
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* CELL: fix colormask code generationRobert Ellison2008-09-231-83/+78
| | | | | | | | | The colormask code generation had assumed that its input packed pixels were in RGBA format. In fact, the format they're in is dependent on the pipe color format. Now the color format is passed in to gen_colormask(), and proper color format-dependent SPU code is generated.
* CELL: improve legibility of CELL_DEBUG environment variable outputRobert Ellison2008-09-231-1/+13
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* cell: Fixed bug with absolute, negate, set-negative logic in source fetch ↵Jonathan White2008-09-221-9/+5
| | | | | | for TGSI instructions. The logic should operate on the origin channel not the swizzled channel. Please enter the commit message for your changes.
* cell: Added TRUNC, SWZ (extended) and XPD instructions, verified against ↵Jonathan White2008-09-221-45/+156
| | | | softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH.
* cell: Added DPH instruction and verified against softpipe.Jonathan White2008-09-221-0/+41
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* cell: use different opcodes for spe_move() depending on even/odd addressBrian Paul2008-09-191-1/+7
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* cell: make sure the fragment ops and fragment shader code buffer is at a ↵Brian Paul2008-09-192-5/+7
| | | | | | 32-byte boundary To make sure even/odd instructions hit the right pipes.
* gallium: added ALIGN32_ATTRIBBrian Paul2008-09-191-0/+2
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* gallium: added spe_code_size()Brian Paul2008-09-192-0/+8
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* cell: Added FRC instructionJonathan White2008-09-191-0/+41
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* cell: Added FLR instruction. Verified the following instructions match ↵Jonathan White2008-09-191-9/+20
| | | | softpipe: MOV, ADD, MUL, SGE, SUB, MAD, ABS, SLT, MIN, MAX, LRP, DP3, DP4, CMP, FLR
* cell: Fixed bugs with DP3 and DP4, they match softpipe results now.Jonathan White2008-09-191-3/+37
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* cell: flesh out support for other Z/stencil formatBrian Paul2008-09-191-36/+64
| | | | | Also: improve float/int Z conversion. Use clgt instead of cgt in depth test since we're comparing unsigned values.
* cell: issue warning to stderr when using fallback fragment opsBrian Paul2008-09-191-1/+9
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* cell: fix a commentBrian Paul2008-09-191-1/+1
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* cell: the test for CELL_DEBUG_FRAGMENT_OP_FALLBACK in ↵Brian Paul2008-09-191-1/+1
| | | | cmd_state_fragment_ops() was inverted
* cell: disable XShmPutImage for tiled surface for nowBrian Paul2008-09-191-2/+2
| | | | Multiple displays of same surface data causes pixels to get scrambled.
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