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* radeonsi: remove upload code for zero-stride vertex attribsMarek Olšák2017-05-101-26/+8
| | | | | | | st/mesa takes care of it now. Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEXMarek Olšák2017-05-1017-0/+18
| | | | | | | The next patch will use it. This is really for svga and GL2-level drivers. Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: remove pipe_index_buffer and set_index_bufferMarek Olšák2017-05-10105-1160/+627
| | | | | | | | | | | | | | pipe_draw_info::indexed is replaced with index_size. index_size == 0 means non-indexed. Instead of pipe_index_buffer::offset, pipe_draw_info::start is used. For indexed indirect draws, pipe_draw_info::start is added to the indirect start. This is the only case when "start" affects indirect draws. pipe_draw_info::index is a union. Use either index::resource or index::user depending on the value of pipe_draw_info::has_user_indices. v2: fixes for nine, svga
* gallium: separate indirect stuff from pipe_draw_info - 80 -> 56 bytesMarek Olšák2017-05-1013-105/+141
| | | | For faster initialization of non-indirect draws.
* gallium: decrease the size of pipe_vertex_buffer - 24 -> 16 bytesMarek Olšák2017-05-1075-338/+372
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* radeonsi: silent a compiler warningSamuel Pitoiset2017-05-101-1/+1
| | | | | | | | | | | | | | This fixes: si_shader.c: In function ‘si_shader_dump_stats’: si_shader.c:6704:31: warning: passing argument 1 of ‘si_get_max_workgroup_size’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] si_get_max_workgroup_size(shader); ^~~~~~ si_shader.c:5832:17: note: expected ‘struct si_shader *’ but argument is of type ‘const struct si_shader *’ static unsigned si_get_max_workgroup_size(struct si_shader *shader) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: dump compute descriptor listsNicolai Hähnle2017-05-101-0/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: dump both enabled and required descriptor slotsNicolai Hähnle2017-05-101-6/+12
| | | | | | This allows a meaningful dump with info == NULL (for compute shaders). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: dump compute shader as part of debug dumpNicolai Hähnle2017-05-101-0/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move struct si_compute into a headerNicolai Hähnle2017-05-103-21/+52
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: split descriptor list dumpingNicolai Hähnle2017-05-101-16/+21
| | | | | | Prepare for dumping CS descriptor list. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: split shader dumpingNicolai Hähnle2017-05-101-12/+18
| | | | | | Prepare for dumping compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: more const qualifiers in shader dump functionsNicolai Hähnle2017-05-102-12/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: implement dd_dump_launch_gridNicolai Hähnle2017-05-102-1/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: extract dd_dump_shaderNicolai Hähnle2017-05-101-74/+82
| | | | | | Will be re-used for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: dump tokens in util_dump_shader_state only if type is TGSINicolai Hähnle2017-05-101-5/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: add util_dump_grid_infoNicolai Hähnle2017-05-102-0/+30
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-095-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b changed the shader_info from being embedded into being just a pointer. The idea was that sharing the shader_info between NIR and GLSL would be easier if it were a pointer pointing to the same shader_info struct. This, however, has caused a few problems: 1) There are many things which generate NIR without GLSL. This means we have to support both NIR shaders which come from GLSL and ones that don't and need to have an info elsewhere. 2) The solution to (1) raises all sorts of ownership issues which have to be resolved with ralloc_parent checks. 3) Ever since 00620782c92100d77c660f9783504c6d80fa1d58, we've been using nir_gather_info to fill out the final shader_info. Thanks to cloning and the above ownership issues, the nir_shader::info may not point back to the gl_shader anymore and so we have to do a copy of the shader_info from NIR back to GLSL anyway. All of these issues go away if we just embed the shader_info in the nir_shader. There's a little downside of having to copy it back after calling nir_gather_info but, as explained above, we have to do that anyway. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno: fix clang error in fd_get_compute_paramRob Herring2017-05-091-1/+1
| | | | | | | | | | | | With commit 10c17f23b752 ("freedreno: core compute state support"), Android builds fail with the following error: external/mesa3d/src/gallium/drivers/freedreno/freedreno_screen.c:610:17: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] sprintf(ret, ir); ^~ Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* swr: fix polygonmode for front==backGeorge Kyriazis2017-05-082-1/+27
| | | | | | | | | | | | | | | | | | | | Rasterizer core only supports polygonmode front==back. Add logic for populating fillMode for the rasterizer only for that case correctly. Provide enum conversion between mesa enums and core enums. The core renders lines/points as tris. Previously, code would enable stipple for polygonmode != FILL. Modify stipple enable logic so that this works correctly. No regressions in vtk tests. Fixes the following piglit tests: pointsprite gl-1.0-edgeflag-const v2: remove cc stable, and remove "not implemented" assert v3: modified commit message Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: support polygonmode pointGeorge Kyriazis2017-05-081-52/+116
| | | | | | | | | | | | | | | Add support for polygonmode point in the binner. This is done by splitting BinPostSetupPoints from BinPoints, so the earlier call can be called from BinTriangles. Setup has already been done at the time BinPostSetupPoints needs to be called. This checkin just adds support in the rasterizer. A separate checkin will add the appropriate driver support. v2: remove cc stable v3: modified commit message and subject line Reviewed-by: Bruce Cherniak <[email protected]>
* util: move ALWAYS_INLINE macro to util/macro.hTimothy Arceri2017-05-091-11/+0
| | | | | | | | Also added clang check. macro.h is include by p_compiler.h so no other change is needed. Reviewed-by: Nicolai Hähnle <[email protected]>
* swr: move msaa resolve to generalized StoreTileBruce Cherniak2017-05-083-80/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v3: list piglit tests fixed by this patch. Fixed typo Tim pointed out. v2: Reword commit message to more closely adhere to community guidelines. This patch moves msaa resolve down into core/StoreTiles where the surface format conversion routines are available. The previous "experimental" resolve was limited to 8-bit unsigned render targets. This fixes a number of piglit msaa tests by adding resolve support for all the render target formats we support. Specifically: layered-rendering/gl-layer-render: fail->pass layered-rendering/gl-layer-render-storage: fail->pass multisample-formats *[2,4,8,16] gl_arb_texture_rg: crash->pass multisample-formats *[2,4,8,16] gl_ext_texture_snorm: crash->pass multisample-formats *[2,4,8,16] gl_arb_texture_float: fail->pass multisample-formats *[2,4,8,16] gl_arb_texture_rg-float: fail->pass MSAA is still disabled by default, but can be enabled with "export SWR_MSAA_MAX_COUNT=4" (1,2,4,8,16 are options) The default is 0, which is disabled. This patch improves the number of multisample-formats supported by swr, and fixes several crashes currently in the 17.1 branch. Therefore, it should be considered for inclusion in the 17.1 stable release. Being disabled by default, it poses no risk to most users of swr. Reviewed-by: Tim Rowley <[email protected]> cc: [email protected]
* radeonsi: rename si_eliminate_const_vs_outputs -> si_optimize_vs_outputsMarek Olšák2017-05-081-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: split per-patch from per-vertex indicesNicolai Hähnle2017-05-083-21/+42
| | | | | | | Make it a bit clearer that the index spaces are logically seperate by having them defined in different functions. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: clarify documentation of existing SI workaroundNicolai Hähnle2017-05-081-1/+3
| | | | | | | Limiting LS-HS to a single wave is required on all SI chips due to an issue with a power management feature. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix gl_PrimitiveID in tessellation with instanced draws on SINicolai Hähnle2017-05-081-0/+14
| | | | | Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: load patch_id for TES-as-ES when exporting for PSNicolai Hähnle2017-05-081-2/+2
| | | | | | | For some reason, this change is only necessary on SI. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix primitive ID in fragment shader when using tessellationNicolai Hähnle2017-05-081-10/+17
| | | | | | | | | | | In a VS->TCS->TES->PS pipeline, the primitive ID is read from TES exports, so it is as if TES were using the primitive ID. Specifically, this fixes a bug where the primitive ID is not reset at the start of a new instance. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: mark fast-cleared textures as compressed when dirtyingNicolai Hähnle2017-05-081-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | There are a bunch of piglit fast clear tests that regressed on SI, for example ./bin/ext_framebuffer_multisample-fast-clear single-sample. The problem is that a texture is bound as a framebuffer, cleared, and then rendered from in a loop that loops through different clear colors. The texture is never rebound during all this, so the change to tex->dirty_level_mask during fast clear was not taken into account when checking for compressed textures. I have considered simply reverting the problematic commit. However, I think this solution is better. It does require looping through all bound textures after a fast clear, but the alternative would require visiting more textures needless on every draw. Draws are much more common than clears. Note that the rendering feedback loop rules do not apply here, because the framebuffer binding is changed between the glClear and the draw that samples from the texture that was cleared. Fixes: bdd644976952 ("radeonsi: don't mark non-dirty textures with CMASK as compressed") Cc: 17.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50/ir: Replace NV50_PROGRAM_IR_* by PIPE_SHADER_IR_*Pierre Moreau2017-05-075-10/+7
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Remove unused translation methodsPierre Moreau2017-05-072-10/+3
| | | | | | | This code was merged commented out, and has stayed that way ever since. Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Free target if we failed to create a programPierre Moreau2017-05-071-1/+3
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Fail if encountering unknown shader typePierre Moreau2017-05-071-2/+2
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* Revert "radeonsi: constify a bunch of the perfcounter structs."Marek Olšák2017-05-063-46/+52
| | | | | | | This reverts commit 7088b655e8828bb960f528dd33132de27c505b8f. It breaks performance counters. If you use them with this commit, they hang the machine hard. Sysrq and ssh don't work.
* Revert "radeonsi: fix build with GCC 4.8"Marek Olšák2017-05-061-1/+1
| | | | | | This reverts commit 485ece83aceb3a35792efbc6fe2bca57ba46c04a. It's needed to revert 7088b655e8828bb960f528dd33132de27c505b8f.
* freedreno/a3xx: fix hang w/ large render targets and small gmemRob Clark2017-05-063-0/+7
| | | | | | | | | Possibly other gen's have a similar limit. Fixes glmark2 -b shadow with larger resolutions on devices with small gmem (for example, fullscreen 1080p on 8x16/db410c). Cc: [email protected] Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add macro to declare variable length arraysRob Clark2017-05-061-18/+21
| | | | | | We have enough of these, that we should stop open coding this. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: apply the tess+GS hang workaround to Polaris12 as wellMarek Olšák2017-05-051-1/+2
| | | | | | Cc: 17.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix build with GCC 4.8Samuel Pitoiset2017-05-051-1/+1
| | | | | | | Fixes: 7088b655e8 ("radeonsi: constify a bunch of the perfcounter structs.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100937 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: fix Polaris12 (RX 550) breakageMarek Olšák2017-05-051-0/+1
| | | | | | | reported by Greg White. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100892 Cc: 17.1 <[email protected]>
* radeonsi/gfx9: allow the scratch buffer in HS and GSMarek Olšák2017-05-051-10/+0
| | | | | | It works now. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: prevent race conditions when doing scratch patchingMarek Olšák2017-05-051-2/+30
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: separate scratch state patching code into its own functionMarek Olšák2017-05-051-46/+55
| | | | | | | Picked from a different branch. When we stop using the scratch patching, this function will not be called. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: also apply scratch relocations to the 1st shader of merged ↵Marek Olšák2017-05-051-0/+3
| | | | | | shaders Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set correct LLVM calling conventions for merged shadersMarek Olšák2017-05-052-2/+18
| | | | | | for scratch support Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove unused parameters from si_shader_apply_scratch_relocsMarek Olšák2017-05-054-10/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: inline si_llvm_shader_type into si_llvm_create_funcMarek Olšák2017-05-053-33/+22
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use util_memcpy_cpu_to_le32 for shader uploadsMarek Olšák2017-05-051-7/+8
| | | | | | at least I think this is correct. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: make si_compile_llvm staticMarek Olšák2017-05-052-16/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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