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* radeonsi/gfx9: fix bad LLVM params in monolithic LS+HSMarek Olšák2018-04-031-1/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* nir+drivers: add helpers to get # of src/dest componentsRob Clark2018-04-031-5/+1
| | | | | | | | | Add helpers to get the number of src/dest components for an intrinsic, and update spots that were open-coding this logic to use the helpers instead. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: fix fallout of unused false-depth eliminationRob Clark2018-04-032-17/+19
| | | | | | | | | | Since we were MARK flag for both preventing loops, and tracking whether instructions were used, we could end up in an infinite loop due to bd2ca2bcdd. Instead invert the logic.. mark all instructions UNUSED up front and clear the flag as we visit them. Fixes: bd2ca2bcdd freedreno/ir3: eliminate unused false-deps Signed-off-by: Rob Clark <[email protected]>
* gallium/pipebuffer: fix parenthesis locationTimothy Arceri2018-04-031-1/+1
| | | | | | | | | | Without this the return value will never get set to -1. This was first added in 49866c8f3457 and copied in 2b396eeed983. Fixes: 2b396eeed983 "gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342
* gallivm: Fix include for LLVMAddPromoteMemoryToRegisterPassMike Lothian2018-04-021-0/+3
| | | | | | | | | Include llvm-c/Transforms/Utils.h with the newest LLVM 7 Signed-of-by: Mike Lothian <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Fix include for LLVMAddPromoteMemoryToRegisterPassMike Lothian2018-04-021-0/+3
| | | | | | | | | Include llvm-c/Transforms/Utils.h with the newest LLVM 7 Signed-of-by: Mike Lothian <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* st/dri: Initialise modifier to INVALID for DRI2Daniel Stone2018-04-021-0/+1
| | | | | | | | | | | | | | | When allocating a buffer for DRI2, set the modifier to INVALID to inform the backend that we have no supplied modifiers and it should do its own thing. The missed initialisation forced linear, even if the implementation had made other decisions. This resulted in VC4 DRI2 clients failing with: Modifier 0x0 vs. tiling (0x700000000000001) mismatch Signed-off-by: Daniel Stone <[email protected]> Reported-by: Andreas Müller <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Fixes: 3f8513172ff6 ("gallium/winsys/drm: introduce modifier field to winsys_handle")
* radeonsi: implement GL_KHR_blend_equation_advancedMarek Olšák2018-04-0212-17/+203
| | | | | | | MSAA is supported using sample shading. Layered rendering and all texture targets are also supported. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: rename unpack_param -> si_unpack_paramMarek Olšák2018-04-022-27/+31
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: move FMASK shader logic to shared codeMarek Olšák2018-04-021-72/+2
| | | | | | We'll need it for FBFETCH in both TGSI and NIR paths. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: add R600_DEBUG=nofmask to disable MSAA compressionMarek Olšák2018-04-025-14/+17
| | | | | | For testing. Tested-by: Dieter Nützel <[email protected]>
* gallium/u_tests: test FBFETCH and shader-based blending with MSAAMarek Olšák2018-04-021-40/+128
| | | | Tested-by: Dieter Nützel <[email protected]>
* ac/gpu_info: rename has_virtual_memory -> r600_has_virtual_memoryMarek Olšák2018-04-026-23/+23
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* radeonsi/nir: fix explicit component packing for geom/tess doublesTimothy Arceri2018-04-021-8/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: gather buffers declared more accurately and use const fast pathTimothy Arceri2018-04-022-6/+90
| | | | | | | | For now we skip SI && HAVE_LLVM < 0x0600 for simplicity. We also skip setting the more accurate masks for builtin uniforms for now as it causes some piglit regressions. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: create load_const_buffer_desc_fast_path() helperTimothy Arceri2018-04-021-39/+49
| | | | | | | | This will be shared by the TGSI and NIR backends. For simplicity we leave the SI LLVM 5.0 and lower work around only in the TGSI backend. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADERTimothy Arceri2018-04-021-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a5xx: don't align height for PIPE_BUFFERRob Clark2018-04-011-1/+1
| | | | | | | | | Buffers can be large, so we probably don't want to make them all 32x bigger. But they can't be rendered to (at least in GL) so we don't need this workaround to prevent page faults on mem<->gmem. Cc: "18.0" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix page faults on last levelRob Clark2018-04-011-0/+10
| | | | | | | | | | We could alternatively fall back to using "old style" draw's for mem<->gmem (ie. what <= a4xx do) when height is not aligned to 32, but that is somewhat more work (and not really something that could be applied to stable) Cc: "18.0" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix issue w/ glamor composite shadersRob Clark2018-03-312-2/+36
| | | | | | | | | | | | | | | Fixes an issue that became possible when we started lowering phi webs to regs (a7ea2b4e) (although was not really seen until we also switched to using peephole select pass (ec8bc54a) instead of lowering *all* if/else to select). If texture coord (or anything else that uses create_collect() to collect scalar values in a sequence of scalar registers) was consuming a value produced on either side of an if/else (ie. a phi lowered to nir reg, which in ir3 is an "array" of length 1) then register allocation would happen incorrectly and we'd end up sampling from garbage coordinates. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more half-precision fixesRob Clark2018-03-312-8/+37
| | | | | | | | Some instructions require src/dst to be in full or half precision register depending on src/dst type. So do a better job of propagating register type. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add helper to create immed of specified sizeRob Clark2018-03-311-4/+11
| | | | | | | We'll also need to be able to create a half-precision immediate. So re-work create_immed(). Prep work for following patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: pass ctx instead of block to create_collect()Rob Clark2018-03-311-18/+19
| | | | | | Prep work for following patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: eliminate unused false-depsRob Clark2018-03-312-11/+31
| | | | | | | | | | | | | | Previously false-dependencies would get flagged as used, even if the only "use" was a false dep to (for example) prevent a load from being scheduled after a store. In addition to being pointless instructions, in some cases they can cause problems. For example, ldg (and similar instructions) depend on an immed arg getting CP'd into the instruction, but this doesn't happen if an instruction is otherwise unused. Which can result in undefined results (overwriting unintended registers). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add local_group_sizeRob Clark2018-03-313-2/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: clear SSA flag when assigning "ARRAY" regs tooRob Clark2018-03-311-0/+1
| | | | | | Avoids a misleading "INVALID FLAGS" warning in debug builds. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: print array live rangesRob Clark2018-03-311-4/+10
| | | | | | This is also useful to see if optmsgs are enabled. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: Implement DP2 instructionWladimir J. van der Laan2018-03-311-0/+21
| | | | | | | | Use DOT2ADDv instruction with 0.0f constant add. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: implement SEQ/SNE instructionsWladimir J. van der Laan2018-03-311-3/+20
| | | | | | | | | Extend translate_sge_slt to emit these, in analogous fashion but using CNDEv. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Compressed textures supportWladimir J. van der Laan2018-03-311-0/+11
| | | | | | | | | | | | | | Add support for: - PIPE_FORMAT_ETC1_RGB8 - PIPE_FORMAT_DXT1_RGB - PIPE_FORMAT_DXT1_RGBA - PIPE_FORMAT_DXT3_RGBA - PIPE_FORMAT_DXT5_RGBA Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Support TEXTURE_RECTWladimir J. van der Laan2018-03-313-1/+4
| | | | | | | | | Denormalized texture coordinates are required for text rendering in GALLIUM_HUD. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Prevent crash in emit_texture if view is not setWladimir J. van der Laan2018-03-311-3/+10
| | | | | | | | | | Textures will sometimes be updated if texture view state was un-set, without this change that causes an assertion crash or segfault. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Fix fd2_tex_swizWladimir J. van der Laan2018-03-311-9/+9
| | | | | | | | | | | Compose swizzles using util_format_compose_swizzles instead of the custom code (which somehow had a bug). This makes the GL_ALPHA internal format work. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Change use of BLEND_ to BLEND2_Wladimir J. van der Laan2018-03-311-2/+2
| | | | | | | | | | | | | | | Change use of BLEND_ to BLEND2_, BLEND_* a3xx_rb_blend_opcode BLEND2_* is a2xx_rb_blend_opcode This makes no effective difference as the used enumerant has the same value (0), but the other enumerants do not match 1-to-1 so this will avoid future problems. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: Update rnndb header for formats enumerationWladimir J. van der Laan2018-03-311-20/+13
| | | | | | | | | | The format enumeration comes comes from the yamoto register headers that are part of the amd-gpu kernel driver. (see freedreno envytools commit b8fb7978e7ae106d0d11d0b238ab2ba2d4dd9d43) Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* st/wgl: check if WGL_SWAP_INTERVAL is defined in wglSwapIntervalEXT()Brian Paul2018-03-302-2/+2
| | | | | | | | | | | | This allows the WGL_SWAP_INTERVAL env var to override any application calls to wglSwapIntervalEXT(). Useful for debugging, or to set the interval to zero to effectively disable the swap interval. Note: we also rename the previous instance of SVGA_SWAP_INTERVAL to WGL_SWAP_INTERVAL since this is a WGL feature and not related to the svga driver. Reviewed-by: Charmaine Lee <[email protected]>
* spirv: Fix building with SConsNeil Roberts2018-03-305-1/+9
| | | | | | | | | | | | | The SCons build broke with commit ba975140d3c9 because a SPIR-V function is called from Mesa main. This adds a convenience library for SPIR-V and adds it to everything that was including nir. It also adds both nir and spirv to drivers/x11/SConscript. Also add nir/spirv modules to osmesa and libgl-gdi targets. (Brian Paul) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105817 Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* util: Add and use util_is_power_of_two_nonzeroIan Romanick2018-03-291-1/+1
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* util: Move util_is_power_of_two to bitscan.h and rename to ↵Ian Romanick2018-03-2925-51/+45
| | | | | | | | | | | util_is_power_of_two_or_zero The new name make the zero-input behavior more obvious. The next patch adds a new function with different zero-input behavior. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* meson: use dep_libdrm version for pkg-configDylan Baker2018-03-291-1/+1
| | | | | | | | | This corrects pkg-config to use the libdrm version (as computed by the previous patch) instead of using a hardcoded value that may or may not (probably not) be right. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* nvc0/ir: fix emiting NOTs with predicatesKarol Herbst2018-03-291-0/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* broadcom/vc5: Fix setup of integer surface clear values.Eric Anholt2018-03-281-8/+8
| | | | | | | | I'm disappointed that the compiler didn't warn me about use of uninitialized uc in these paths. Just use the incoming clear color instead of the packing temporary if we're doing our own packing. Fixes GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_*
* broadcom/vc5: Stop trying to swizzle around RGBA4 clear color.Eric Anholt2018-03-281-12/+2
| | | | | | | | We always want A in the A slot in the tile buffer, and any other swapping should happen elsewhere. Fixes RGBA4-using cases in fbo-clear-formats and GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_fixed.
* broadcom/vc5: Work around scissor w/h==0 bug same as rasterizer discard.Eric Anholt2018-03-281-2/+15
| | | | | The 7268 HW apparently lets some rendering through in this case. Fixes GTF-GLES2.gtf.GL2FixedTests.scissor.scissor
* radeonsi: simplify DCC format categoriesMarek Olšák2018-03-281-20/+9
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use the SPI barrier management bug workaroundMarek Olšák2018-03-281-0/+5
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: use maximum OFFCHIP_BUFFERING on Vega12Marek Olšák2018-03-281-1/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: add support for Vega12Marek Olšák2018-03-284-1/+7
| | | | Reviewed-by: Alex Deucher <[email protected]>
* broadcom/vc5: Fix padding of NPOT miplevels >= 2.Eric Anholt2018-03-271-3/+8
| | | | | | | The power-of-two padded size that gets minified is based on level 1's dimensions, not level 0's, which starts to differ at a width of 9. Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1
* ac/radeonsi: pass bindless bool to load_sampler_desc()Timothy Arceri2018-03-281-1/+1
| | | | | | | | We also fix the base_index for bindless by using the driver location. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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