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* gallium/radeon: assume X11 DRI3 can use at most 5 back buffersMarek Olšák2016-06-291-1/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: separate DCC starts as disabled (ps_draw_ratio = 0)Marek Olšák2016-06-291-9/+10
| | | | | | | | | | | | | | DRI3: - Only slows clears can enable it for the first frame. - A good PS/draw ratio can enable it for other frames. DRI2: - Only slows clears can enable it for a frame. - Page-flipped color buffers are unref'd at the end of each frame, so it can't be enabled in any other way. - Relying on slow clears is sufficient for our synthetic benchmarks. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: R600_DEBUG=nodccfb disables separate DCCMarek Olšák2016-06-293-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add and use r600_texture_referenceMarek Olšák2016-06-295-10/+13
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a HUD query for PS draw ratio stats from separate DCCMarek Olšák2016-06-294-0/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a heuristic enabling DCC for scanout surfaces (v2)Marek Olšák2016-06-296-4/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCC for displayable surfaces is allocated in a separate buffer and is enabled or disabled based on PS invocations from 2 frames ago (to let queries go idle) and the number of slow clears from the current frame. At least an equivalent of 5 fullscreen draws or slow clears must be done to enable DCC. (PS invocations / (width * height) + num_slow_clears >= 5) Pipeline statistic queries are always active if a color buffer that can have separate DCC is bound, even if separate DCC is disabled. That means the window color buffer is always monitored and DCC is enabled only when the situation is right. The tracking of per-texture queries in r600_common_context is quite ugly, but I don't see a better way. The first fast clear always enables DCC. DCC decompression can disable it. A later fast clear can enable it again. Enable/disable typically happens only once per frame. The impact is expected to be negligible because games usually don't have a high level of overdraw. DCC usually activates when too much blending is happening (smoke rendering) or when testing glClear performance and CMASK isn't supported (Stoney). v2: rename stuff, add assertions Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add state setup for a separate DCC bufferMarek Olšák2016-06-294-5/+41
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: always calculate DCC info even if it's not used immediatelyMarek Olšák2016-06-292-2/+2
| | | | | | for a later use Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unreference framebuffer state with set_framebuffer_stateMarek Olšák2016-06-293-4/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add flag R600_QUERY_HW_FLAG_BEGIN_RESUMESMarek Olšák2016-06-292-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't advertise multisample shader imagesMarek Olšák2016-06-291-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable distributed tess on multi-SE parts onlyMarek Olšák2016-06-294-2/+7
| | | | | | | ported from Vulkan Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set optimal VGT_HS_OFFCHIP_PARAMMarek Olšák2016-06-295-14/+49
| | | | | | | ported from Vulkan Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable CU0 in each SE for LS-HS executionMarek Olšák2016-06-291-2/+1
| | | | | | | Offchip-only tessellation allows this. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use conformant line rasterizationMarek Olšák2016-06-294-5/+29
| | | | | | | | | | AA lines are not completely correct (see TODO), but everything else should be. + 3 linestipple piglits Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* svga: force direct map for transfering multiple slicesCharmaine Lee2016-06-281-15/+24
| | | | | | | | | | | | | With commit fb9fe35, we start using transfer_inline_write for memcpy of TexSubImage. But SurfaceDMA command does not work well with texture array. This patch forces direct map when transfering multiple slices of a texture array. Fixes piglit regression "texelFetch fs sampler1DArray" Tested with MTT piglit, glretrace, conform. Reviewed-by: Sinclair Yeh <[email protected]>
* svga: whitespace, line wrapping fixes in svga_surface.cBrian Paul2016-06-281-11/+16
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* gm107/ir: make sure that flagsDef is set when emitting setcondSamuel Pitoiset2016-06-281-1/+1
| | | | | | | | | | | Rely on the existence of a second destination when emitting a setcond flag is dangerous, because this doesn't mean that the flag has been correctly set. Instead rely on flagsDef like what emitX() does for flagsSrc. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* radeonsi: set PA_SU_SMALL_PRIM_FILTER_CNTL register on PolarisMarek Olšák2016-06-282-0/+11
| | | | | | | This was missing. Cc: 12.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/vce: use vce structure for vce 52 firmwareBoyuan Zhang2016-06-285-98/+517
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vce: add vce structuresBoyuan Zhang2016-06-281-0/+297
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/omx: fix decoder fillout for the OMX result bufferLeo Liu2016-06-281-4/+5
| | | | | | | | | | | | | The call for vl_video_buffer_adjust_size is with wrong order of arguments, apparently it will have problem when interlaced false; The size of OMX result buffer depends on real size of clips, vl buffer dimension is aligned with 16, so 1080p(1920*1080) video will overflow the OMX buffer Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Julien Isorce <[email protected]>
* pipe_loader_sw: Fix fd leak when instantiated via pipe_loader_sw_probe_kmsHans de Goede2016-06-281-0/+7
| | | | | | | | | | | | Make pipe_loader_sw_probe_kms take ownership of the passed in fd, like pipe_loader_drm_probe_fd does. The only caller is dri_kms_init_screen which passes in a dupped fd, just like dri2_init_screen passes in a dupped fd to pipe_loader_drm_probe_fd. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* clover: Fix kernel metadata retrieval after clang r273425Jan Vesely2016-06-271-4/+31
| | | | | Signed-off-by: Jan Vesely <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* clover/llvm: Fix copyright attribution of invocation.cpp.Francisco Jerez2016-06-271-1/+5
| | | | | | | | | | This file still only has my name on the copyright notice even though most of the code (likely more than 90% of it) was authored by various contributors -- It doesn't seem right to have the whole file attributed to myself. Acked-by: Michel Dänzer <[email protected]> Acked-by: Serge Martin <[email protected]>
* gm107/ir: add missing setcond flags for LOP variantsSamuel Pitoiset2016-06-281-0/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* gm107/ir: make use of LOP32I for all immediatesSamuel Pitoiset2016-06-281-1/+1
| | | | | | | | LOP only allows to emit 19-bits immediates. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* virgl: reduce some limits for nowDave Airlie2016-06-281-3/+4
| | | | | | | | | These need to be passed from the host in caps structure if they are larger, this fixes a bunch of tests on Intel hw, that I'd put the limits too high for. Cc: "11.2 12.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/omx: count number of slicesJulien Isorce2016-06-271-0/+3
| | | | | | | | | Used by nouveau driver. Similar patch was done for st/va: 851e7e12aa628d6781b5a3af2f2fc16ee73f435f Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx: add support for nouveau / interlacedJulien Isorce2016-06-271-25/+26
| | | | | Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx: retrieve preferred interlaced and buffer_formatsJulien Isorce2016-06-271-2/+24
| | | | | | | Interlaced can be true for nouveau driver. Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: use optimal WD settings for primitive restart on PolarisMarek Olšák2016-06-271-2/+10
| | | | | | ported from Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* st/va: Check NULL pointerGurkirpal Singh2016-06-271-0/+4
| | | | | | | | | | Call to handle_table_get in vlVaDestroySurfaces can return NULL on failure. CID: 1243522 Signed-off-by: Gurkirpal Singh <[email protected]> Reviewed-by: Julien Isorce <[email protected]>
* gm107/ir: make use of MOV32I for all immediatesSamuel Pitoiset2016-06-271-2/+1
| | | | | | | | | MOV only allows to emit 19-bits immediates. This is similar to the previous fix I did for IMUL. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nvc0: update "derived" state function namesIlia Mirkin2016-06-261-8/+8
| | | | | | | derived_1/2/etc aren't too informative. Instead name them based on the state they're derived from. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: provide support for unscaled poly offset unitsIlia Mirkin2016-06-263-3/+26
| | | | | | | | On at least Kepler hardware, the units differ based on RT format. Emit a properly scaled value for Z16 depth buffers vs other formats, to help out st/nine. Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: make use of IMUL32I for all immediatesSamuel Pitoiset2016-06-261-1/+1
| | | | | | | | | | IMUL only allows to emit 19-bits immediates. This is similar to d30768025a2283d4cc57930b784798bf278969da which fixed the same thing for the GK110 emitter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* radeonsi: make si_is_format_supported staticMarek Olšák2016-06-253-11/+6
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-254-15/+15
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-259-75/+75
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-259-132/+134
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use r600_resource_referenceMarek Olšák2016-06-2512-40/+32
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/nine: Use offset_units_unscaledAxel Davy2016-06-255-11/+13
| | | | | | | | | | | | offset_units_unscaled enables proper support for depth bias for gallium nine. Use it if available. Solves issues with some games using depth bias. For example: https://github.com/iXit/Mesa-3D/issues/220 Signed-off-by: Axel Davy <[email protected]>
* r600g: Implement POLYGON_OFFSET_UNITS_UNSCALEDAxel Davy2016-06-255-36/+46
| | | | | | | | | | | | | | | | Empirical tests show that the polygon offset behaviour is entirely determined by the content of the PA_SU_POLY_OFFSET states, and not by the depth buffer format bound. PA_SU_POLY_OFFSET seems to directly set the parameters of the polygon offset formula, and setting 0 for PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled behaviour. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALEDAxel Davy2016-06-252-15/+19
| | | | | | | | | | | | | | | | Empirical tests show that the polygon offset behaviour is entirely determined by the content of the PA_SU_POLY_OFFSET states, and not by the depth buffer format bound. PA_SU_POLY_OFFSET seems to directly set the parameters of the polygon offset formula, and setting 0 for PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled behaviour. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon: Remove useless pa_su_poly_offset_db_fmt_cntlAxel Davy2016-06-251-1/+0
| | | | | | | | pa_su_poly_offset_db_fmt_cntl usages were removed in previous patches. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreenAxel Davy2016-06-251-25/+13
| | | | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. v2: Increase the num_dw field for the poly offset atom Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600Axel Davy2016-06-251-24/+13
| | | | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. v2: Increase the num_dw field for the poly offset atom Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset statesAxel Davy2016-06-251-23/+8
| | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with rasterizer poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add a cap for offset_units_unscaledAxel Davy2016-06-2519-0/+31
| | | | | | | | | | | | | | D3D9 has a different behaviour for depth bias. For OGL/D3D1X, the depth bias unit is the minimal resolvable value for the depth buffer, which depends on the format (and has different behaviour for float depth buffers). For D3D9, the depth bias unit is 1.0f. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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