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* r600g: reduce quant mode on evergreen+Alex Deucher2012-09-131-1/+1
| | | | | | | | | | Seems to have an affect on the allowable range of values. Set evergreen+ to 1/256 to match 6xx/7xx. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54877 Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: don't use a staging resource for large transfersMarek Olšák2012-09-131-10/+0
| | | | It kills performance if the resource is linear.
* r600g: don't use a staging resource for large transfersMarek Olšák2012-09-131-10/+0
| | | | It kills performance if the resource is linear.
* r600g: convert the remnants of VGT state into immediate register writes/atoms v4Marek Olšák2012-09-138-57/+65
| | | | | | | | | v2: Group vgt register together to avoid lockup v3: Split multi primitive register and index bias register v4: Bump R600_NUM_ATOMS Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: emit the primitive type and associated regs only if the type is changedMarek Olšák2012-09-135-48/+38
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: add clip_misc_state for clip registers emitted in draw_vboMarek Olšák2012-09-138-22/+44
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix computing how much space is needed for a draw commandMarek Olšák2012-09-132-6/+12
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix the number of CS dwords of cb_misc_stateMarek Olšák2012-09-132-2/+2
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize clip stateMarek Olšák2012-09-136-148/+38
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize blend colorMarek Olšák2012-09-136-27/+25
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize viewport stateMarek Olšák2012-09-137-40/+28
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize stencil ref stateMarek Olšák2012-09-137-51/+56
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: remove unused state ID definitionsMarek Olšák2012-09-131-8/+0
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: initialize the first CS just like any other CSMarek Olšák2012-09-136-26/+24
| | | | | | by reusing the CS initialization in r600_context_flush. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: add support for geometry shader samplers and constant buffersMarek Olšák2012-09-135-1/+52
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: put sampler states and views into an array indexed by shader typeMarek Olšák2012-09-136-72/+44
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: do fine-grained sampler state updatesMarek Olšák2012-09-136-51/+110
| | | | | | | | | | | | Update only those sampler states which are changed in a shader stage, instead of always updating all sampler states in the shader stage. That requires keeping a bitmask of those states which are enabled, and those states which are dirty at a given point (subset of enabled states). This is similar to how sampler views, constant buffers, and vertex buffers are handled. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: consolidate set_viewport_state functionsMarek Olšák2012-09-133-48/+24
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: consolidate set_sampler_views functionsMarek Olšák2012-09-134-38/+17
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: put constant buffer state into an array indexed by shader typeMarek Olšák2012-09-136-40/+33
| | | | | | to easily and robustly handle multiple shader stages Reviewed-by: Jerome Glisse <[email protected]>
* r600g: cleanup state function namesMarek Olšák2012-09-133-37/+37
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: consolidate initialization of common state functionsMarek Olšák2012-09-135-150/+81
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: simplify flushingMarek Olšák2012-09-1312-190/+210
| | | | | | | | | | | | Based on the patch called "simplify and fix flushing and synchronization" by Jerome Glisse. Rebased, removed unneded code, simplified more and cleaned up. Also, SH_ACTION_ENA is not set when changing shaders (hw doesn't seem to need it). It's only used to flush constant buffers. Reviewed-by: Jerome Glisse <[email protected]>
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-137-93/+19
| | | | | | Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns.
* radeon/llvm: Support fmul on SITom Stellard2012-09-131-1/+4
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* radeonsi: Properly handle NULL sampler views.Michel Dänzer2012-09-121-3/+3
| | | | | | | | | | Fixes piglit shaders/glsl-fs-uniform-sampler-array and many other similar tests. In fact, I just completed a piglit quick-driver.tests run without any GPU lockups or even VM protection faults. Yay! Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Fix calculation of number of records in buffer resource.Michel Dänzer2012-09-121-1/+1
| | | | | | | | | | | The value was too small by 1 in some cases (non-first of several vertex elements interleaved in a single buffer). Fixes intermittent incorrect geometry in many apps, e.g. piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Assert if we try to encode an unknown registerTom Stellard2012-09-111-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Ignore special registers when calculating reg countTom Stellard2012-09-111-0/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-114-1/+53
| | | | | | | | v2: - Don't increment ninterp or set any of the have_* flags for TGSI_SEMANTIC_POSITION Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-112-12/+21
| | | | | | | The compiler needs to know which interpolation modes are enabled, so it knows which values will be preloaded into the VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Add missing interpolation mode to check for enabled modesTom Stellard2012-09-111-0/+1
| | | | | | | At least one interpolation mode must be enable, but the code that checks this was not checking for perspective center. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: Pass shader type to the compilerTom Stellard2012-09-111-0/+12
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
| | | | | | | This allows the program to specify the type of shader being compiled (e.g. PXEL, VERTEX, etc.) Reviewed-by: Michel Dänzer <[email protected]>
* r600g: avoid GPU doing constant preload from random addressJerome Glisse2012-09-112-0/+40
| | | | | | | | | Previous command stream might have set any of the constant buffer and the previous address might no longer be valid thus GPU might preload constant from random invalid address and possibly triggering lockup. Signed-off-by: Jerome Glisse <[email protected]>
* radeonsi: Texture border colour fixes.Michel Dänzer2012-09-113-8/+56
| | | | | | | | | | * Handle arbitrary border colours. * Use correct packing format for detecting special border colours. Fixes piglit tex-border-1 and probably many other tests using border colours. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Handle NULL sampler states.Michel Dänzer2012-09-111-1/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove unused functionMarek Olšák2012-09-112-22/+0
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* r600g: fix printf warningMarek Olšák2012-09-111-1/+2
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* nvc0/ir: add initial code to support GK110 ISA encodingChristoph Bumiller2012-09-0710-13/+1691
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* radeonsi: Float format fixups.Michel Dänzer2012-09-071-1/+24
| | | | | | Fixes piglit spec/ARB_texture_float/fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Handle more SNORM formats.Michel Dänzer2012-09-071-0/+22
| | | | | | | Fixes piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats (except for what seems like a random fluke). Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Handle TGSI_SEMANTIC_FOG.Michel Dänzer2012-09-071-0/+1
| | | | | | | | | Fixes exponential fog. The pixel shaders for linear fog seem to get miscompiled still somehow. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
| | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: order atom emission v3Jerome Glisse2012-09-067-82/+116
| | | | | | | | | | | | | To avoid GPU lockup registers must be emited in a specific order (no kidding ...). This patch rework atom emission so order in which atom are emited in respect to each other is always the same. We don't have any informations on what is the correct order so order will need to be infered from fglrx command stream. v2: add comment warning that atom order should not be taken lightly v3: rebase on top of alphatest atom fix Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix num of dwords needed for alphatest_state atomJerome Glisse2012-09-061-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Make driver name more informative.José Fonseca2012-09-061-1/+4
| | | | | | | | | | | | | | | Such as "llvmpipe (LLVM 3.1, 128 bits)" or "llvmpipe (LLVM 3.1, 256 bits)" when leveraging AVX 8-wide registers. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
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