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* radeonsi: fix stupid bug added in commit ↵Christian König2012-08-301-7/+8
| | | | | | | 07838603b9a69c05911edbcd351bfce5ad9b5a2c Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
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* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
| | | | | | | | | | | The Common Subexpression Elimination pass will not operate on instructions with physical register defs, so we end up with several redundant copies to M0 when using interpolation. Adding a register class that only contains the M0 register allows use to use a virtual register to represent M0, and makes it possible for the Common Subexpression Elimination pass to remove the extra copies.
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
| | | | | This flag makes these instructions candidates for the dead code elimination and common subexpression elimination.
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-293-3/+4
| | | | | This signals to the Dead Code Elimination pass that it is safe to remove these instructions when they are dead.
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
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* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
| | | | | | | Fixes piglit fp-kil and glBitmap() with radeonsi. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Basic support for SI EXEC register.Michel Dänzer2012-08-283-2/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Don't write to the PA_SC_RASTER_CONFIG register.Michel Dänzer2012-08-281-1/+0
| | | | | | | It should be initialized by the kernel as necessary. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: fix relative addressing on RS780 and RS880Marek Olšák2012-08-281-7/+6
| | | | | | They should be treated like RV670. Tested-by: Michel Dänzer <[email protected]>
* llvmpipe: Bump the maximum texture size (in pixels).José Fonseca2012-08-282-2/+9
| | | | | | | | | | But cap the size in bytes, to avoid depleting the whole system memory, with humongus textures. Tested with max-texture-size piglit test. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* u_vbuf: avoid unnecessary update of the vertex elementsVadim Girlin2012-08-281-1/+3
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: implement tile code for PIPE_FORMAT_Z32_FLOATBrian Paul2012-08-271-0/+36
| | | | Reviewed-by: José Fonseca <[email protected]>
* r300g: implement TRUNC correctlyMarek Olšák2012-08-274-1/+42
| | | | This fixes some integer division tests.
* radeonsi: Use FP16 shader export format when necessary / possible.Michel Dänzer2012-08-276-18/+114
| | | | | | | | | Fixes piglit fbo-blending-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Refactor initialization of shader export intrinsic arguments.Michel Dänzer2012-08-271-36/+48
| | | | | | | | | In preparation for extending this code, which would make it rather unwieldy in its current place. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Maintain cache of pixel shader variants according to contxt state.Michel Dänzer2012-08-276-59/+210
| | | | | | | | | Mostly inspired by r600g commit 4acf71f01ea1edb253cd38cc059d4af1a2a40bf4 ('r600g: cache shader variants instead of rebuilding v3'). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Drop extraneous semicolons from pm4 state macro definitions.Michel Dänzer2012-08-271-3/+3
| | | | | | | | Could cause build failures if trying to use the macros in certain constructs. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement compression for MSAA colorbuffers for evergreenMarek Olšák2012-08-2712-19/+529
| | | | | | | | | | | | | | | | This adds the FMASK and CMASK buffers. They share the same resource with color data. COMPRESSION and FAST_CLEAR are always enabled if both FMASK and CMASK are allocated. We initialize the CMASK to a "compressed" state (not "fast cleared"), so that we can keep FAST_CLEAR enabled all the time. Both FMASK and CMASK must be present at the moment. If either one is missing, the other one is not used. v2: add cayman regs in the list Reviewed-by: Jerome Glisse <[email protected]>
* r600g: cleanup names around depth decompressionMarek Olšák2012-08-275-24/+24
| | | | | | for consistency with the upcoming color decompression naming Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix evergreen 8x MSAA sample positionsMarek Olšák2012-08-271-16/+16
| | | | | | | The original samples positions took samples outside of the pixel boundary, leading to dark pixels on the edge of the colorbuffer, among other things. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: set CB_TARGET_MASK to 0xf and not 0xff for resolve on evergreenMarek Olšák2012-08-271-0/+1
| | | | | | | independent_blend_enable must be true, so that the colormask isn't replicated in all colorbuffers. Reviewed-by: Jerome Glisse <[email protected]>
* gallium/u_blitter: initialize sample mask in resolveMarek Olšák2012-08-271-0/+1
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r300/compiler: Use variable lists in the rename_regs passTom Stellard2012-08-261-17/+14
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* st/dri: Support width and height gettersJakob Bornecrantz2012-08-261-1/+7
| | | | | Tested-by: Scott Moreau <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* st/dri: Claim to support validate_usageJakob Bornecrantz2012-08-261-1/+16
| | | | | | | | Support version 3 as well as 2, since that is only the new format query, which Jesse added support for to st/dri when he added it to dri_inteface.h. Tested-by: Scott Moreau <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* wgl: update some commentsBrian Paul2012-08-242-2/+2
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* radeonsi: remove old tilling handlingChristian König2012-08-243-279/+31
| | | | | | | | | Just use the functionality provided by the surface manager instead. This fixes just another bunch of piglit tests. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* clover: Accept CL_MEM_READ_WRITE flagBlaž Tomažič2012-08-241-4/+4
| | | | | | | Fix API functions for memory objects to accept CL_MEM_READ_WRITE flag. Signed-off-by: Blaž Tomažič <[email protected]> [ Francisco Jerez: Drop incorrect change in clCreateSubBuffer. ]
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-242-93/+28
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* draw: Fix regression in draw_set_sampler(_views).José Fonseca2012-08-241-6/+6
| | | | | | | | | | draw->samplers(_views) now has PIPE_SHADER_TYPES elements, instead of PIPE_MAX_SAMPLERS as before. Also, shader_stage must be less than PIPE_SHADER_TYPES to prevent buffer overflow. Trivial.
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-233-10/+14
| | | | This code was accidently dropped during the MCCodeEmitter conversion.
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
| | | | | This should fix an assertion failure that was happening in some compute shaders.
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-2314-82/+135
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* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-2321-76/+38
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* radeon/llvm: Simplify the convert to ISA passTom Stellard2012-08-233-20/+7
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* radeon/llvm: Make sure to use the Text section in the AsmPrinterTom Stellard2012-08-231-0/+2
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* st/dri: pass config options to the state trackerVadim Girlin2012-08-231-0/+8
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* st/mesa: accept and handle configuration options from st/driVadim Girlin2012-08-231-0/+14
| | | | | | Currently there is a single option - force_glsl_extensions_warn. Signed-off-by: Vadim Girlin <[email protected]>
* st/dri: add force_glsl_extensions_warn option to dri optionsVadim Girlin2012-08-231-1/+10
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* st/dri: use driver name for driconf section lookupVadim Girlin2012-08-231-1/+2
| | | | | | | The name is taken from the driver_descriptor, so it will be the same as expected by driconf utility. Signed-off-by: Vadim Girlin <[email protected]>
* swrast: add DRM_DRIVER_DESCRIPTOR to store driver nameVadim Girlin2012-08-231-0/+3
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* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-2316-738/+779
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* radeon/llvm: Use the MCCodeEmitter for SITom Stellard2012-08-2315-431/+591
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* radeon/llvm: Set 64BitPtr feature bit for SITom Stellard2012-08-231-1/+1
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* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-233-8/+12
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* radeon/llvm: Add AsmPrinterTom Stellard2012-08-238-0/+193
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* radeon/llvm: Mark JUMP as a pseudo instructionTom Stellard2012-08-231-1/+1
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* radeon/llvm: Remove the last uses of MachineOperand flagsTom Stellard2012-08-232-8/+27
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* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-237-33/+97
| | | | | | | This new operand replaces the MachineOperand flags in LLVM, which will be deprecated soon. Eventually all instructions should have a flag operand, but for now this operand has only been added to instructions that need it.
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