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* svga: Tell the host to discard when doing writes without FLUSH_EXPLICIT.José Fonseca2011-03-151-3/+10
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* svga: Update svga_winsys_screen::buffer_map comments.José Fonseca2011-03-151-2/+2
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* svga: Ensure DMA commands are serialized with unsynchronized flag is unset.José Fonseca2011-03-153-19/+113
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* r300g: implement the texture barrierMarek Olšák2011-03-151-0/+10
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* gallium: add texture barrier support to the interface and st/mesa (v2)Marek Olšák2011-03-152-0/+15
| | | | v2: change the gallium entry point to texture_barrier.
* gallium/util: Use PIPE_TRANSFER_DISCARD_RANGE in pipe_buffer_write.Mathias Fröhlich2011-03-151-0/+2
| | | | | | | | Additionally, to discarding the whole buffer, use PIPE_TRANSFER_DISCARD_RANGE in pipe_buffer_write when the write covers only part of the buffer. Signed-off-by: Mathias Fröhlich <[email protected]>
* r600g: FLT_TO_INT_FLOOR and FLT_TO_INT_RPI are vector-only instructions on ↵Henri Verbeet2011-03-151-3/+6
| | | | | | Evergreen. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: fix logic error in 028987c80362eddd39176628486a456b076f0427Alex Deucher2011-03-141-1/+1
| | | | | | Spotted by Henri on IRC. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't set per-MRT blend bits on R600Alex Deucher2011-03-141-5/+10
| | | | | | | | | It doesn't support them. Also, we shouldn't be emitting CB_BLENDx_CONTROL on R600 as the regs don't exist there, but I'm not sure of the best way to deal with this in the current r600 winsys. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Original R600 does not support per-MRT blendsAlex Deucher2011-03-141-2/+11
| | | | | | Only rv6xx+ support them. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit SURFACE_BASE_UPDATE packet on rv6xxAlex Deucher2011-03-142-2/+25
| | | | | | | | This packet is required when updating the DB, CB, or STRMOUT base addresses on rv6xx for the surface sync logic to work correctly. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().Henri Verbeet2011-03-142-8/+7
| | | | | | | This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again, but that's not something we want to depend on. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Fix the DB_SHADER_CONTROL mask in create_ds_state().Henri Verbeet2011-03-142-10/+8
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Properly update DB_SHADER_CONTROL in evergreen_pipe_shader_ps().Henri Verbeet2011-03-141-18/+14
| | | | | | | Disable Z_EXPORT / STENCIL_EXPORT / KILL_ENABLE again if a shader doesn't use those. This is similar to 0a6f09a76a416b8672e149c520aa5bef33174223. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet2011-03-146-31/+32
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_ps() to r600_state.c.Henri Verbeet2011-03-143-95/+97
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_vs() to r600_state.c.Henri Verbeet2011-03-143-49/+49
| | | | | | | | The idea behind this is that anything touching registers should be in r600_state.c or evergreen_state.c. This is also consistent with evergreen_pipe_shader_vs(). Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Evergreen add support for log opcode.Rafael Monica2011-03-141-1/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r300g: clamp after blending for fixed-point formats onlyMarek Olšák2011-03-143-14/+36
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* gallivm: Fix build with llvm 2.6 on 32bit platformsJosé Fonseca2011-03-131-2/+4
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* gallivm: Use LLVM MC disassembler, instead of udis86.José Fonseca2011-03-137-227/+369
| | | | | Included in LLVM 2.7+. Unlink udis86, should support all instructions that LLVM can emit.
* util: Silence gcc unitialized member warningJosé Fonseca2011-03-131-0/+1
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* draw: Fix draw_variant_output::format's type.José Fonseca2011-03-132-3/+4
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* nv50,nvc0: don't assert on cso with 0 vertex elementsChristoph Bumiller2011-03-133-6/+2
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* rbug: Use the call mutexJakob Bornecrantz2011-03-131-19/+187
| | | | Fixes crashes in [soft|llvm]pipe when replacing shaders
* r600g: Only update DB_SHADER_CONTROL once in r600_pipe_shader_ps().Mathias Fröhlich2011-03-131-16/+13
| | | | | | | | | Avoid setting the same gpu register several times in a r600_pipe_state. Compute the final value of the register and set that one time. This avoids some overhead in r600_context_pipe_state_set(). Signed-off-by: Mathias Fröhlich <[email protected]> Signed-off-by: Henri Verbeet <[email protected]>
* tgsi: Fix parsing of properties with digits in the nameJakob Bornecrantz2011-03-131-1/+1
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* rbug: Skip drawing on disabled shadersJakob Bornecrantz2011-03-131-1/+4
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* rbug: Remove flags from flushJakob Bornecrantz2011-03-132-6/+0
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* i915g: Lie more so we get GLSLJakob Bornecrantz2011-03-131-2/+3
| | | | Lots of piglit tests are lazy and wants GLSL
* i915g: Point sprite cap could be supportedJakob Bornecrantz2011-03-131-1/+2
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* i915g: Sort cap listJakob Bornecrantz2011-03-131-1/+1
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* nvc0: support edge flagsChristoph Bumiller2011-03-134-14/+88
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* nvc0: fix POLYGON_MODE_BACK macro copy/paste errorChristoph Bumiller2011-03-131-1/+1
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* nv50,nvc0: fix pipe context switchChristoph Bumiller2011-03-132-10/+64
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* nv50,nvc0: clean up flushesChristoph Bumiller2011-03-135-38/+28
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* nv50,nvc0: add some missing resource referencingChristoph Bumiller2011-03-134-7/+64
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* nvc0: mask out centroid bit for writing FP headerChristoph Bumiller2011-03-131-1/+1
| | | | It's only 2 bit per input, centroid is set in the instruction.
* nvc0: identify VERTEX_QUARANTINEChristoph Bumiller2011-03-133-8/+17
| | | | | | | | Well, not sure what exactly it is, but it certainly doesn't contain the control flow stack, but vertex data. Not sure about size, I've only seen the first few KiB written, but the binary driver seems to allocate more.
* nvc0: don't enable early-z if alpha test is enabledChristoph Bumiller2011-03-134-12/+20
| | | | | | Depth values are also written before the shader is executed, so if early tests are enabled, fragments that failed the alpha test were modifying the depth buffer, but they shouldn't.
* nvc0: move sprite coord replace state into csoChristoph Bumiller2011-03-132-27/+8
| | | | It's not dependent on any other state anymore now.
* nvc0: s/nblocksx/nblocksy for height in resource_copy_regionChristoph Bumiller2011-03-131-1/+1
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* nvc0: fix unitialized variable in TGSI sysval decl processingChristoph Bumiller2011-03-131-0/+1
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* nvc0: update/fix supported instruction src modifiersChristoph Bumiller2011-03-135-20/+31
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* i915g: fix transfer coherencyDaniel Vetter2011-03-123-26/+7
| | | | | | | | | | | | The kernel drm takes care of all coherency as long as we don't forget to submit all outstanding commands in the batchbuffer ... Also move batchbuffer initialization up because otherwise transfers for some helper textures fail with a segmentation fault. And kill the dead code, flushes should now be correct everywhere. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: don't recalculate fb dimensionDaniel Vetter2011-03-123-31/+4
| | | | | | The statetracker should do this for us correctly. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: use y-tiling when the blitter is not usedDaniel Vetter2011-03-121-1/+4
| | | | | | The blitter is broken. Who'd have guessed? Signed-off-by: Daniel Vetter <[email protected]>
* i915g: implement copy_region using u_blitterDaniel Vetter2011-03-124-9/+128
| | | | Signed-off-by: Daniel Vetter <[email protected]>works
* i915g: fix use after freeDaniel Vetter2011-03-122-3/+3
| | | | | | | Pipe templates should be copied if still needed after the create call completes. Signed-off-by: Daniel Vetter <[email protected]>
* gallium: Delay the creation of simple helper shadersJakob Bornecrantz2011-03-122-80/+116
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