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* vc4: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]>
* ilo: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Chia-I Wu <[email protected]>
* freedreno: unref old fenceRob Clark2015-07-101-1/+3
| | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]>
* gallium: clarify reference counting for fenceRob Clark2015-07-101-1/+7
| | | | | | | | | Nowhere was it spelled out that the state tracker may expect the pipe driver to unref the old fence. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* xa: don't leak fencesRob Clark2015-07-103-3/+7
| | | | | | | | | | | | XA was never unref'ing last_fence in the various call paths to pipe->flush(). Add this to xa_context_flush() and update the other open-coded calls to pipe->flush() to use xa_context_flush() instead. This fixes a memory leak reported with xf86-video-freedreno. Reported-by: Nicolas Dechesne <[email protected]> Cc: "10.5 10.6" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* tgsi: whitespace fixes in tgsi_parse.cBrian Paul2015-07-091-13/+13
| | | | Trivial.
* gallium: fix comment typo in p_shader_tokens.hBrian Paul2015-07-091-1/+1
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* gallium/docs: s/treaded/treated/ typo in tgsi.rstBrian Paul2015-07-091-1/+1
| | | | Trivial.
* st/vdpau: fix mixer size checksChristian König2015-07-091-11/+11
| | | | | | | | We need to check what the 3D pipe is able to handle for the mixer, not what the decoder is able to decode. This fixes output of resolutions like 720x1280. Signed-off-by: Christian König <[email protected]> CC: [email protected]
* vl: cleanup video buffer private when the decoder is destroyedChristian König2015-07-092-0/+28
| | | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=90728 Signed-off-by: Christian König <[email protected]> CC: [email protected]
* nv50: avoid segfault with enabled but unbound vertex attribSamuel Pitoiset2015-07-081-0/+5
| | | | | | | | | | | Before validating vertex arrays we need to check if a VBO is present. Checking if vb->buffer is not NULL fixes the issue. Fixes the following piglit test: gl-3.1-vao-broken-attrib Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix wrong use of BLIT_SRC_Y_INT for 2D texture copySamuel Pitoiset2015-07-081-1/+1
| | | | | | | | | | According to nv50, this should be src->ms_y instead of src->ms_x. This code is here since 2012, so it's probably a typo error which has never been detected since a long time. I didn't do a full piglit run to check if it fixes some other weird issues. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* android: freedreno: add missing components to the buildVarad Gautam2015-07-081-1/+4
| | | | | | | Freedreno requires {a4xx,ir3}_SOURCES and NIR to build. Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nvc0: turn sample counts off during blitIlia Mirkin2015-07-071-0/+7
| | | | | | | | | Fixes the following piglits: occlusion_query_meta_fragments occlusion_query_meta_no_fragments Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* st/dri: don't set PIPE_BIND_SCANOUT for MSAA surfacesMarek Olšák2015-07-071-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91231 Reviewed-by: Brian Paul <[email protected]>
* gallium/hud: display percentages with % suffixBrian Paul2015-07-071-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: add PIPE_DRIVER_QUERY_TYPE_MICROSECONDS for HUDBrian Paul2015-07-072-10/+26
| | | | | | | | This allows drivers to report queries in units of microseconds and have the HUD display "us" (microseconds), "ms" (milliseconds) or "s" (seconds) on the graph. Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: replace byte units flag with pipe_driver_query_typeBrian Paul2015-07-073-16/+18
| | | | | | | Instead of using a boolean 'is bytes' value, use the pipe_driver_query_type enum type. This will let is add support for time values in the next patch. Reviewed-by: Marek Olšák <[email protected]>
* gallium/os: minor whitespace fixes in os_time.hBrian Paul2015-07-071-5/+6
| | | | Trivial.
* radeonsi: Use param export count from si_llvm_export_vs in si_shader_vsMichel Dänzer2015-07-073-22/+6
| | | | | | | | | | | | This eliminates the error prone logic in si_shader_vs recalculating this value. It also fixes TGSI_SEMANTIC_CLIPDIST outputs incorrectly not being counted for VS exports. They need to be counted because they are passed to the pixel shader as parameters as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91193 Reviewed-by: Marek Olšák <[email protected]>
* gallivm: fix lp_build_compare_extRoland Scheidegger2015-07-062-1/+4
| | | | | | | | | | | | The expansion should always be to the same width as the input arguments no matter what, since these functions should work with any bit width of the arguments (the sext is a no-op on any sane simd architecture). Thus, fix the caller expecting differently. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=91222 Tested-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* winsys/radeon: use os_wait_until_zero in radeon_bo_set_tilingMarek Olšák2015-07-051-3/+1
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* radeonsi: don't flush an empty IB if the only thing we need is a fenceMarek Olšák2015-07-053-3/+15
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/os: add conversion and wait functions for absolute timeoutsMarek Olšák2015-07-052-0/+67
| | | | | | | | Absolute timeouts are used with the amdgpu kernel driver. It also makes waiting for several variables and fences at the same time easier (the timeout doesn't have to be recalculated after every wait call). Reviewed-by: Alex Deucher <[email protected]>
* gallium/os: add os_wait_until_zero (v2)Marek Olšák2015-07-052-1/+48
| | | | | | | | | | This will be used by radeon and amdgpu winsyses. Copied from the amdgpu winsys. v2: use volatile and p_atomic_read Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: mark the gpu load thread stop trigger as volatileMarek Olšák2015-07-051-1/+1
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* gallium: remove redundant pipe_context::fence_signalledMarek Olšák2015-07-0513-131/+0
| | | | | | fence_finish(timeout=0) does the same thing Reviewed-by: Brian Paul <[email protected]>
* gallium: use fence_finish instead of fence_signalled in state trackersMarek Olšák2015-07-054-4/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium: handle fence_finish timeout in various driversMarek Olšák2015-07-055-0/+15
| | | | | | I copied what fence_signalled does. Reviewed-by: Brian Paul <[email protected]>
* gallium/docs: remove out-of-date document about D3D11 featuresMarek Olšák2015-07-051-462/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* radeonsi: fix a hang with DrawTransformFeedback on 4 SE chipsMarek Olšák2015-07-051-0/+4
| | | | | | Cc: 10.6 10.5 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* nv50/ir: UCMP arguments are float, so make sure modifiers are appliedIlia Mirkin2015-07-031-1/+2
| | | | | | | | | The first argument to UCMP needs to be compared against 0, but the latter arguments are treated as float and need to be able to properly apply neg/abs arguments. Adjust the inferSrcType function accordingly. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.Mario Kleiner2015-07-031-3/+10
| | | | | | | | | | | | | | Same problem and fix as for nouveau's ZaphodHeads trouble. See patch ... "nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads." ... for reference. Cc: "10.3 10.4 10.5 10.6" <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: disable single-sample fast color clear due to hangsMarek Olšák2015-07-031-1/+6
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73528 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82186 Cc: 10.4 10.5 10.6 <[email protected]>
* r600g,radeonsi: implement get_device_reset_statusMarek Olšák2015-07-036-4/+38
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/ir3: don't be confused by eliminated indirectsRob Clark2015-07-032-0/+14
| | | | | | | | If an instruction using address register value gets eliminated, we need to remove it from the indirects list, otherwise it causes mayhem in sched for scheduling address register usage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sched fixes for addr register usageRob Clark2015-07-031-12/+65
| | | | | | | | | | | | | | | | A handful of fixes and cleanups: 1) If we split addr/pred, we need the newly created instruction to end up in the unscheduled_list 2) Avoid scheduling a write to the address register if there is no instruction using the address register that is otherwise ready to schedule. Note that I currently don't bother with the same logic for predicate register, since the only instructions using predicate (br/kill) don't take any other src registers, so this situation should not arise. 3) few other cosmetic cleanups Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix indirects trackingRob Clark2015-07-035-10/+23
| | | | | | | | | | cp would update instr->address but not update the indirects array resulting in sched getting confused when it had to 'spill' the address register. Add an ir3_instr_set_address() helper to set instr->address and also update ir->indirects, and update all places that were writing instr->address to use helper instead. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: mark location specially in nir for color0-writes-allIlia Mirkin2015-07-033-1/+16
| | | | | | | | | | We need to distinguish a shader that has separate writes to each MRT from one which is supposed to write the data from MRT 0 to all the MRTs. In TGSI this is done with a property. NIR doesn't have that, so encode it as a funny location and decode on the other end. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: IN/OUT are only array if ArrayID != 0Rob Clark2015-07-031-62/+81
| | | | | | | | Fixes issue with gallium HUD. See this thread for details: http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* tgsi: update docs for ArrayID usageRob Clark2015-07-031-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50/ir: don't emit src2 in immediate formIlia Mirkin2015-07-021-2/+2
| | | | | | | | | In the immediate form, src2 == dst, so it does not need to be emitted. Otherwise it overlaps with the immediate value's low bits. Fixes: 09ee907266 (nv50/ir: Fold IMM into MAD) Cc: "10.6" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capabilityAlexandre Courbot2015-07-011-1/+2
| | | | | | | | | | Prefer blit-based texture transfers only if the chip has dedicated VRAM since it would translate to a copy into the same memory on shared-memory chips. Signed-off-by: Alexandre Courbot <[email protected]> Reported-by: Ilia Mirkin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: create screen fence objects with coherent attributeAlexandre Courbot2015-07-021-2/+6
| | | | | | | | | | | | | | | This is required on non-coherent architectures to ensure the value of the fence is correct at all times. Failure to do this results in the display freezing for a few seconds every now and then on Tegra. The NOUVEAU_BO_COHERENT is a no-op for coherent architectures, so behavior on x86 should not be affected by this patch. Also bump the required libdrm version to 2.4.62, which introduced this flag. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* ilo: remove ilo_image_paramsChia-I Wu2015-07-011-75/+47
| | | | It suffices to use ilo_image_layout directly.
* ilo: add image_init_gen6_transfer_layout()Chia-I Wu2015-07-011-75/+37
| | | | It replaces img_init_for_transfer().
* ilo: add image_set_gen6_bo_size()Chia-I Wu2015-07-013-118/+89
| | | | It replaces img_calculate_bo_size().
* ilo: add image_set_gen6_{hiz,mcs}Chia-I Wu2015-07-011-49/+61
| | | | They replace img_calculate_{hiz,mcs}_size().
* ilo: add image_get_gen6_monolithic_size()Chia-I Wu2015-07-011-67/+67
| | | | It replaces img_align().
* ilo: add image_get_gen6_lods()Chia-I Wu2015-07-011-88/+148
| | | | It replaces img_init_lods() and img_init_layer_height().
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