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* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
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* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
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* gallium: mention PIPE_TIMEOUT_INFINITE in the fence_finish() commentBrian Paul2012-09-201-1/+1
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* llvmpipe: fix overflow bug in total texture size computationBrian Paul2012-09-201-2/+16
| | | | | | | | | | | | | | | | v2: use uint64_t for the total_size variable, per Jose. Also add two earlier checks for exceeding the max texture size. For example a 1K^3 RGBA volume would overflow the lpr->image_stride variable. Use simple algebra to avoid overflow in intermediate values. So instead of "x * y > z" use "x > z / y". This should work if we happen to be on a platform that doesn't have 64-bit types. Reviewed-by: Jose Fonseca <[email protected]>
* r600g/llvm: rs780/rs880 are r600 asicsAlex Deucher2012-09-201-2/+2
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r300/compiler: Use precomputed q values in the register allocatorTom Stellard2012-09-191-1/+69
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* r300g: Init regalloc state during context creationTom Stellard2012-09-198-155/+204
| | | | | | Initializing the regalloc state is expensive, and since it is always the same for every compile we only need to initialize it once per context. This should help improve shader compile times for the driver.
* r300/compiler: Don't create register classes for inputsTom Stellard2012-09-191-14/+1
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* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-191-1/+1
| | | | | | This allows the user to pass precomputed q values to the allocator. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: Invalidate texture cache when creating vertex buffers for compute v2Tom Stellard2012-09-191-1/+3
| | | | | | | | | | | Compute shaders fetch data from vertex buffers via the texture cache, so we need to make sure the texture cache is flushed. v2: - Fix rebase mistake - Fix spelling in comment Reviewed-by: Marek Olšák <[email protected]>
* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-193-2/+11
| | | | | | | | | | LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited to 4096 iterations like the other LOOP_* instructions. Compute shaders need to use this instruction, and since we aren't optimizing loops with the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like we should just use it for everything. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Set the correct value of COLOR*_DIM for RATsTom Stellard2012-09-191-2/+2
| | | | | | | | | For buffers (which is what is being used for RATs), the COLOR*_DIM.WIDTH_MASK field needs to be set to the low 16-bits of the buffer size, and the COLOR*_DIM.HEIEGHT_MAX needs to be set to the high bits. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Make sure to initialize DB_DEPTH_CONTROL register for computeTom Stellard2012-09-191-1/+3
| | | | | | The kernel CS checker will fail if this register is not initialized. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add some comments and debug printfs to compute codeTom Stellard2012-09-192-5/+53
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add missing break to case statementTom Stellard2012-09-191-0/+1
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* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-1910-167/+359
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
| | | | | This is necessary upcoming encoding changes, since we will only be using 9-bits for register encoding.
* winsys/radeon: fix relocs cachingVadim Girlin2012-09-192-8/+6
| | | | | | | | | | | Don't cache pointers to elements of reallocatable array. In some circumstances it caused false cache hits resulting in incorrect command stream and gpu lockup. Note: This is a candidate for the stable branches. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add a fdiv pattern.Vincent Lejeune2012-09-181-3/+10
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* radeon/llvm: reserve also corresponding 128bits regVincent Lejeune2012-09-181-0/+1
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* softpipe: implement the new can_create_resource() functionBrian Paul2012-09-172-5/+29
| | | | | | And define a SP_MAX_TEXTURE_SIZE value as we do in llvmpipe. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: implement the new can_create_resource() functionBrian Paul2012-09-171-5/+23
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gallium: add new pipe_screen::can_create_resource() functionBrian Paul2012-09-172-0/+18
| | | | | | | | | | Used to implement proxy textures. If a gallium driver doesn't implement this function we'll just continue to use the core Mesa fallback code. Without this hook we really have no good way to implement OpenGL proxy textures with gallium drivers. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: set max cube texture size to 4K x 4KBrian Paul2012-09-172-1/+2
| | | | | | | | Before, the limit was 8K. For 32-bit RGBA that would be require 1.5 GB of memory (w/out mipmaps). That's well beyond the LP_MAX_TEXTURE_SIZE of 1GB. Reviewed-by: Jose Fonseca <[email protected]>
* radeon/llvm: Inital flow control support for SITom Stellard2012-09-177-2/+168
| | | | | | This adds basic flow control support for If-Then-Else blocks using predicates (stored in the EXEC register) and a predicate stack for nested flow control.
* r600g: Close a memory leak of llvm byte streamsXinya Zhang2012-09-171-0/+1
| | | | | | | No regressions found in the tests of opencl-example/run_tests.sh. Signed-off-by: Xinya Zhang <[email protected]> Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
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* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-176-470/+35
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* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Match vector logical operations on SI.Michel Dänzer2012-09-171-3/+9
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* softpipe: update SP_MAX_TEXTURE_3D_LEVELS commentBrian Paul2012-09-161-1/+1
| | | | 9 levels = max size of 256 texels.
* Temporarily revert "mesa: remove remaining FEATURE_* defines where protected ↵José Fonseca2012-09-151-0/+2
| | | | | | | | by API check." This reverts commit 9f37b405a3de8668a5f74c9681829688475ac3b7. Fixes windows builds.
* mesa: remove remaining FEATURE_* defines where protected by API check.Oliver McFadden2012-09-151-2/+0
| | | | | Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Support frint on SIChristian König2012-09-141-1/+3
| | | | | | | | Gets VDPAUs shaders working again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: consolidate decompression code for the blitterMarek Olšák2012-09-141-29/+37
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* r600g: do not require MSAA renderbuffer support if not asked forMarek Olšák2012-09-142-16/+4
| | | | | | to allow stencil-only sampler-only formats (like X24S8) NOTE: This is a candidate for the stable branches.
* gallium/u_blitter: fix stencil-only blitsMarek Olšák2012-09-141-0/+15
| | | | NOTE: This is a candidate for the stable branches.
* r300g: fix colormask with non-BGRA formatsMarek Olšák2012-09-144-31/+160
| | | | NOTE: This is a candidate for the stable branches.
* r600g: reduce quant mode on evergreen+Alex Deucher2012-09-131-1/+1
| | | | | | | | | | Seems to have an affect on the allowable range of values. Set evergreen+ to 1/256 to match 6xx/7xx. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54877 Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: don't use a staging resource for large transfersMarek Olšák2012-09-131-10/+0
| | | | It kills performance if the resource is linear.
* r600g: don't use a staging resource for large transfersMarek Olšák2012-09-131-10/+0
| | | | It kills performance if the resource is linear.
* r600g: convert the remnants of VGT state into immediate register writes/atoms v4Marek Olšák2012-09-138-57/+65
| | | | | | | | | v2: Group vgt register together to avoid lockup v3: Split multi primitive register and index bias register v4: Bump R600_NUM_ATOMS Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: emit the primitive type and associated regs only if the type is changedMarek Olšák2012-09-135-48/+38
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: add clip_misc_state for clip registers emitted in draw_vboMarek Olšák2012-09-138-22/+44
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix computing how much space is needed for a draw commandMarek Olšák2012-09-132-6/+12
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: fix the number of CS dwords of cb_misc_stateMarek Olšák2012-09-132-2/+2
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize clip stateMarek Olšák2012-09-136-148/+38
| | | | Reviewed-by: Jerome Glisse <[email protected]>
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