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* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
| | | | This fixes several hundred piglit tests.
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
| | | | | V_CVT_I32_F32 converts floats to signed integers, but we were using V_CVT_F32_I32 which convertes signed integers to float.
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
| | | | | SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
| | | | | | | The CodeEmitter was not setting the VGPR bit for src0, because the instruction definition had the VCC register in the src0 slot, instead of the actual src0 register. This has been fixed by moving the VCC register to the end of the operand list.
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* winsys/radeon: create only one winsys for each fdChristian König2012-09-042-2/+41
| | | | | | | Fixing problems with GLAMOR. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: stop big offsets from hanging the GPU v2Christian König2012-09-041-2/+9
| | | | | | | v2: rebased of radeon/llvm fix. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTSChristian König2012-09-042-5/+2
| | | | | | | So it matches what we really can do. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
| | | | | | | The offset is unsigned, not signed. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallivm,llvmpipe: Use 4-wide vectors on AMD Bulldozer.José Fonseca2012-09-043-1/+15
| | | | | | 8-wide vectors is slower. Reviewed-by: Roland Scheidegger <[email protected]>
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-044-2/+24
| | | | | | | | | Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16. Helps to pass some piglit tests (fbo, multisample). Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* util: Add cpuid for Solaris Studio.Vinson Lee2012-09-032-2/+6
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi: disable array-textures for nowChristian König2012-09-031-1/+1
| | | | Signed-off-by: Christian König <[email protected]>
* radeonsi: disable Z16 for nowChristian König2012-09-031-2/+2
| | | | | | | It's causing crashes. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: disable NPOT textures for nowChristian König2012-09-031-1/+1
| | | | | | | | | Looks like we have an alignment issue with NPOT textures and mipmaps. So disable NPOT textures until we figure out what is going wrong here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: handle indirect constants gracefullyChristian König2012-09-031-0/+7
| | | | | | | It's not supported yet, so at least don't try to crash the box. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* vega: include u_debug.h for assert()Brian Paul2012-09-011-0/+1
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* mesa: s/FREE/free/Brian Paul2012-09-015-16/+16
| | | | | | | v2: replace instances in dri/common/ dirs Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: s/MALLOC/malloc/Brian Paul2012-09-012-3/+3
| | | | | | | v2: replace instances in dri/common/ dirs Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util: remove u_debug.h from u_math.hBrian Paul2012-09-011-1/+0
| | | | No debug code is used in u_math.h
* util: include u_debug.hBrian Paul2012-09-011-0/+1
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* tgsi: include u_debug.hBrian Paul2012-09-011-0/+1
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* dri: Rework planar image interfaceJakob Bornecrantz2012-08-312-1/+82
| | | | | | | | | | | | | | | | | | | | | | As discussed with Kristian on #wayland. Pushes the decision of components into the dri driver giving it greater freedom to allow t to implement YUV samplers in hardware, and which mode to use. This interface will also allow drivers like SVGA to implement YUV surfaces without the need to sub-allocate and instead send 3 seperate buffers for each channel, currently not implemented. I have tested these changes on Gallium Svga. Scott tested them on both intel and Gallium Radeon. Kristan and Pekka tested them on intel. v2: Fix typo in dri2_from_planar. v3: Merge in intel changes. Tested-by: Scott Moreau <[email protected]> Tested-by: Pekka Paalanen <[email protected]> Tested-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-3110-44/+150
| | | | | | | Immediate operands were previously handled in the CodeEmitter, but that code was buggy and very confusing. This commit adds a pass that simplifies the handling of immediate operands by spliting the loading of the immediate into a sperate insruction that is bundled with the original.
* radeon/llvm: Fix typo in assertTom Stellard2012-08-311-1/+1
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* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
| | | | | This predicate incorrectly included SI GPUs, so some Evergreen instructions were being emmitted on SI.
* radeon/llvm: Add support for RCP instruction on SITom Stellard2012-08-311-1/+3
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* radeon/llvm: Support AMDGPUfmin DAG node on SITom Stellard2012-08-311-1/+3
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* radeonsi: Handle TGSI_SEMANTIC_PSIZETom Stellard2012-08-311-0/+1
| | | | | | | | | | The relevant POINT_SIZE registers are being set using the pipe_rasterizer_state, so we just need to tell the shader compiler which export type to use. This fixes several of the glean glsl tests. Reviewed-by: Alex Deucher <[email protected]>
* util: add casts to silence signed/unsigned comparison warningsBrian Paul2012-08-311-2/+2
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* r600g: enable transform feedback on CaymanMarek Olšák2012-08-311-3/+1
| | | | There doesn't seem to be anything wrong with it.
* r600g: implement MSAA for CaymanMarek Olšák2012-08-318-73/+187
| | | | | Everything works except for blitting MSAA colorbuffers, which isn't so trivial on Cayman. It's a rarely-used feature anyway.
* r600g: enable MSAA on r6xx by defaultMarek Olšák2012-08-301-3/+6
| | | | | DRM 2.22.0 is required though. Also require the new DRM for r700, as there are some important fixes for that generation too.
* r600g: disable MSAA depth decompression on r6xxMarek Olšák2012-08-301-1/+10
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* r600g: implement color resolve for r600Marek Olšák2012-08-307-26/+199
| | | | | | | | | The blend state is different and the resolve single-sample buffer must have FMASK and CMASK enabled. I decided to have one CMASK and one FMASK per context instead of per resource. There are new FMASK and CMASK allocation helpers and a new buffer_create helper for that.
* r600g: fix CB_SHADER_MASK and CB_TARGET_MASK for r6xxMarek Olšák2012-08-301-11/+24
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* r600g: implement draw_rectangle callbackMarek Olšák2012-08-305-16/+88
| | | | | | The color resolve on r6xx needs PT_RECTLIST. Using conventional primitive types (triangles and quads) produces an ugly line between two diagonally opposite corners. I guess a rectangular point sprite would work too.
* r600g: implement MSAA for r700Marek Olšák2012-08-307-41/+262
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: change programming of CB_SHADER_MASK on r600-r700Marek Olšák2012-08-301-1/+2
| | | | | | | This one actually makes more sense and gives the expected value for MSAA resolve. Reviewed-by: Jerome Glisse <[email protected]>
* radeonsi: fix stupid bug added in commit ↵Christian König2012-08-301-7/+8
| | | | | | | 07838603b9a69c05911edbcd351bfce5ad9b5a2c Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
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* radeon/llvm: Create a register class for the M0 registerTom Stellard2012-08-295-16/+24
| | | | | | | | | | | The Common Subexpression Elimination pass will not operate on instructions with physical register defs, so we end up with several redundant copies to M0 when using interpolation. Adding a register class that only contains the M0 register allows use to use a virtual register to represent M0, and makes it possible for the Common Subexpression Elimination pass to remove the extra copies.
* radeon/llvm: Set the neverHasSideEffects bit on more instructionsTom Stellard2012-08-291-0/+2
| | | | | This flag makes these instructions candidates for the dead code elimination and common subexpression elimination.
* radeon/llvm: Declare the interpolation intrinsics as ReadOnlyTom Stellard2012-08-293-3/+4
| | | | | This signals to the Dead Code Elimination pass that it is safe to remove these instructions when they are dead.
* radeon/llvm: Mark M0 as a def when lowering interpolation instructionsTom Stellard2012-08-291-4/+2
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* radeon/llvm: Handle TGSI KIL opcode for SI.Michel Dänzer2012-08-283-0/+44
| | | | | | | Fixes piglit fp-kil and glBitmap() with radeonsi. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
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