| Commit message (Collapse) | Author | Age | Files | Lines |
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All flags are set for st/mesa, so the state tracker doesn't have to check
them.
Reviewed-by: Ilia Mirkin <[email protected]>
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Without this patch I get the following during DMA transfers:
[drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream !
radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096)
This is a fixup for e878e154cdfd4dbb5474f776e0a6d86fcb983098.
Signed-off-by: Niels Ole Salscheider <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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Point util_memcpy_cpu_to_le32 to a buffer storage directly.
v2: simplify more
Reviewed-by: Michel Dänzer <[email protected]>
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Trivial.
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Trivial.
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Tahiti has 12 tile pipes, but P8 pipe config.
It looks like there is no way to get the pipe config except for reading
GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes,
so we can't use that for Hawaii.
This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f
on Tahiti.
v2: add an assertion and print an error on failure
Cc: [email protected]
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This will help to get rid of the buffer_get_virtual_address calls.
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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R600-R700 don't support virtual memory.
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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The code is rewritten to take known constraints into account, while always
using 0 by default.
This should improve performance for multi-SE parts in theory.
A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs go away, you have found the problem.)
Reviewed-by: Alex Deucher <[email protected]>
v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
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This isn't documented anywhere, but it's the only thing that works
for this case.
Cc: [email protected]
Reviewed-by: Alex Deucher <[email protected]>
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v2: Rebase on helpers.
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Fixes glean fragProg1's "ADD test" and likely many others.
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These values are supposed to be the minimum/maximum index values used to
read from the vertex buffers. This code either copies index values out of
the old IB (so, same min/max as the original draw call), or generates a
new IB (using index values between the start and the start + count of the
old array draw info, which just happens to be what min/max_index are set
to by st_draw.c).
We were incorrectly setting the max_index in the
converting-from-glDrawArrays case to the start vertex plus the number of
vertices generated in the new IB, which broke QUADS primitive conversion
on VC4 (where max_index really has to be correct, or the kernel might
reject your draw call due to buffer overflow).
Reviewed-by: Rob Clark <[email protected]> (from verbal description
of the patch)
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v2: Rebase on helpers change.
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Some tests start working (useprogram-flushverts, for example) due to
getitng the right vertices now. Some that used to pass start failing with
memory overflow during binning, which is weird (glsl-fs-texture2drect).
And a couple stop rendering correctly (glsl-fs-bug25902).
v2: Move the attribute format setup in the key from after search time to
before the search.
v3: Fix reading of attributes other than position (I forgot to respect
attr and stored everything in inputs 0-3, i.e. position).
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v2: Rebase on helpers.
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v2: Rebase on helpers.
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This avoids a simulator assertion failure with glamor. I need to actually
support resize, though.
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We could get undefined sources in real programs from the wild, so we'll
need to turn off this debug eventually. But for now, using undefined
sources is typically me just mistyping something.
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v2: Fix how it was using the X channel for the real work of the opcode,
instead of Y. Fixes glean's LIT test.
v3: Rebase on the helpers.
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v2: Rebase on helpers.
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I wanted an easy way to set up new uniforms every time, so I could handle
texture-sampler-related uniforms.
v2: Rebase on helpers change.
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v2: Rebase on helpers, cutting out most of the code in this change.
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We put in a bunch of extra MOVs for program outputs, and this can clean
those up. We should do uniforms, too, though.
v2: Fix missing flagging of progress when we actually optimize. Caught by
Aaron Watry.
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This cleans up a bunch of noise in the compiled coordinate shaders (since
we don't need the varying outputs), and also from writemasked instructions
with negated src operands.
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There was a lot of extra noise in my piglit shader dumps because of silly
CMPs.
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This took a couple of tries, and this is the squash of those attempts.
v2: Fix register file conflicts on the args in the
destination-is-accumulator case.
v3: Rebase on helper change and qir_inst4 change.
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This should also be used as a way to pair QIR instructions into QPU
instructions later.
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It doesn't do all the interpolation yet, but more tests can run now.
v2: Rebase on helpers.
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Reserving a whole accumulator for temps is awful in the first place, but
I'll fix that later.
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v2: Rebase on qir helpers.
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We will want to occasionally disable this again when we do clear support.
v2: Squash with the previous commit (I accidentally committed at two
stages of writing the change)
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This was a problem for the simulator since we don't free memory back to
it, and it would soon just run out.
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v2: Fix an accidental deletion of some characters from the copyright
message (caught by Ilia Mirkin)
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This is hardcoded to read it as RGBA32F so far, but starts to get more
tests working.
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We do rely on a real BO getting allocated, so make sure we ask for a non-zero size.
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This introduces an IR (QIR, for QPU IR) to do optimization on. It's a
scalar, SSA IR in general. It looks like optimization is pretty easy this
way, though I haven't figured out if it's going to be good for our weird
register allocation or not (or if I want to reduce to basically QPU
instructions first), and I've got some problems with it having some
multi-QPU-instruction opcodes (SEQ and CMP, for example) which I probably
want to break down.
Of course, this commit mostly doesn't work, since many other things are
still hardwired, like the VBO data.
v2: Rewrite to use a bunch of helpers (qir_OPCODE) for emitting QIR
instructions into temporary values, and make qir_inst4 take the 4 args
separately instead of an array (all later callers wanted individual
args).
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Note: This is the cutoff point where I switched from developing primarily
on the Pi to developing o the simulator. As a result, from this point on
the code is untested on the Pi (the kernel code I have currently wasn't
rendering anything at this commit, though the simulator renders
successfully, suggesting kernel bugs).
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This mostly just takes every draw call and turns it into a sequence of
commands that clear the FBO and draw a single shaded triangle to it,
regardless of the actual input vertices or shaders. I copied the initial
driver skeleton mostly from freedreno, and I've preserved Rob Clark's
copyright for those. I also based my initial hardcoded shaders and
command lists on Scott Mansell (phire)'s "hackdriver" project, though the
bit patterns of the shaders emitted end up being different.
v2: Rebase on gallium megadrivers changes.
v3: Rebase on PIPE_SHADER_CAP_MAX_CONSTS change.
v4: Rely on simpenrose actually being installed when building for
simulation.
v5: Add more header duplicate-include guards.
v6: Apply Emil's review (protection against vc4 sim and ilo at the same
time, and dropping the dricommon drm bits) and fix a copyright header
(thanks, Roland)
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