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* gallium/tgsi: Add resource write-back support.Francisco Jerez2012-05-118-4/+45
| | | | | Define a new STORE opcode with a role dual to the LOAD opcode, and add flags to specify that a shader resource is intended for writing.
* gallium/tgsi: Add support for raw resources.Francisco Jerez2012-05-115-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | Normal resource access (e.g. the LOAD TGSI opcode) is supposed to perform a series of conversions to turn the texture data as it's found in memory into the target data type. In compute programs it's often the case that we only want to access the raw bits as they're stored in some buffer object, and any kind of channel conversion and scaling is harmful or inefficient, especially in implementations that lack proper hardware support to take care of it -- in those cases the conversion has to be implemented in software and it's likely to result in a performance hit even if the pipe_buffer and declaration data types are set up in a way that would just pass the data through. Add a declaration flag that marks a resource as typeless. No channel conversion will be performed in that case, and the X coordinate of the address vector will be interpreted in byte units instead of elements for obvious reasons. This is similar to D3D11's ByteAddressBuffer, and will be used to implement OpenCL's constant arguments. The remaining four compute memory spaces can also be understood as raw resources.
* gallium/tgsi: Define the TGSI_BUFFER texture target.Francisco Jerez2012-05-115-6/+6
| | | | | | This texture type was already referred to by the documentation but it was never defined. Define it as 0 to match the pipe_texture_target enumeration values.
* gallium/tgsi: Introduce the compute processor.Francisco Jerez2012-05-115-4/+9
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* gallium/tgsi: Move interpolation info from tgsi_declaration to a separate token.Francisco Jerez2012-05-1119-74/+141
| | | | | | Move Interpolate, Centroid and CylindricalWrap from tgsi_declaration to a separate token -- they only make sense for FS inputs and we need room for other flags in the top-level declaration token.
* gallium: Add context hooks for binding shader resources.Francisco Jerez2012-05-115-1/+58
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* gallium/tgsi: Split sampler views from shader resources.Francisco Jerez2012-05-1117-183/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit splits the current concept of resource into "sampler views" and "shader resources": "Sampler views" are textures or buffers that are bound to a given shader stage and can be read from in conjunction with a sampler object. They are analogous to OpenGL texture objects or Direct3D SRVs. "Shader resources" are textures or buffers that can be read and written from a shader. There's no support for floating point coordinates, address wrap modes or filtering, and, unlike sampler views, shader resources are global for the whole graphics pipeline. They are analogous to OpenGL image objects (as in ARB_shader_image_load_store) or Direct3D UAVs. Most hardware is likely to implement shader resources and sampler views as separate objects, so, having the distinction at the API level simplifies things slightly for the driver. This patch introduces the SVIEW register file with a declaration token and syntax analogous to the already existing RES register file. After this change, the SAMPLE_* opcodes no longer accept a resource as input, but rather a SVIEW object. To preserve the functionality of reading from a sampler view with integer coordinates, the SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS) but take a SVIEW register instead of a RES register as argument.
* gallium: Basic compute interface.Francisco Jerez2012-05-117-2/+185
| | | | | | | | | | Define an interface that exposes the minimal functionality required to implement some of the popular compute APIs. This commit adds entry points to set the grid layout and other state required to keep track of the usual address spaces employed in compute APIs, to bind a compute program, and execute it on the device. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Properly translate vertex format swizzle.Michel Dänzer2012-05-113-23/+23
| | | | egltri_screen works correctly!
* radeon/llvm: Remove AMDILMCCodeEmitter.cppTom Stellard2012-05-102-158/+0
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* radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* radeonsi: Set NONE format for unused vertex shader position export slots.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Eliminate one more magic number for texture image resources.Michel Dänzer2012-05-101-3/+3
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* radeonsi: Fix vertex buffer resource for stride 0.Michel Dänzer2012-05-101-1/+5
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* radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* svga: implement CEIL opcode translationBrian Paul2012-05-091-0/+28
| | | | Reviewed-by: José Fonseca <[email protected]>
* gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-094-0/+28
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* r600g: Handle TGSI_OPCODE_CEIL (v2)Kai Wasserbäch2012-05-091-3/+3
| | | | | | | v2: Enabled CEIL on Cayman too. Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallivm: implement iabs/issg opcode.Dave Airlie2012-05-092-1/+26
| | | | | | Reimplemented by Olivier Galibert <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-0810-117/+8
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* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-0810-27/+83
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* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
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* radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
| | | | It is no longer used.
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
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* radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
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* radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
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* radeon/llvm: add suport for cube texturesVadim Girlin2012-05-082-23/+91
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-085-21/+63
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-084-13/+293
| | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-086-6/+43
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for VertexID, InstanceIDVadim Girlin2012-05-083-0/+50
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix live-in handling for inputsVadim Girlin2012-05-082-2/+3
| | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: add support for v4i32Vadim Girlin2012-05-084-5/+20
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: fix ABS_i32 instruction loweringVadim Girlin2012-05-081-2/+2
| | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use integer comparison for IFVadim Girlin2012-05-081-2/+4
| | | | | | | Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: use bitcasts for integersVadim Girlin2012-05-083-5/+73
| | | | | | | | | We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: Fix out of tree builds that use the LLVM backendTom Stellard2012-05-071-1/+1
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=49567
* radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()Tom Stellard2012-05-074-22/+3
| | | | | | | These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110