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* swr: only store up to the LOD sizeIlia Mirkin2016-11-291-1/+3
* swr: [rasterizer common] add SwrTrace() and macrosTim Rowley2016-11-292-15/+95
* radeonsi: don't fetch 8 dwords for samplerBuffer and imageBufferMarek Olšák2016-11-291-51/+43
* radeonsi: disable XNACK to free 2 SGPRs on APUsMarek Olšák2016-11-291-1/+1
* radeonsi: count and report temp arrays in scratch separatelyMarek Olšák2016-11-292-4/+40
* radeonsi: don't try to eliminate trivial VS outputs for PS and CSMarek Olšák2016-11-291-1/+4
* radeonsi: disable RB+ blend optimizations for dual source blendingMarek Olšák2016-11-291-0/+11
* radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blendingMarek Olšák2016-11-291-0/+4
* radeonsi: always set all blend registersMarek Olšák2016-11-291-5/+5
* radeonsi: set the smallest possible CB_TARGET_MASKMarek Olšák2016-11-291-5/+5
* radeonsi: don't print bodies of header-only packetsMarek Olšák2016-11-291-0/+4
* radeonsi: print unknown registers with correct formattingMarek Olšák2016-11-291-1/+2
* ddebug: fix hang detection with deferred flushesMarek Olšák2016-11-291-1/+1
* vc4: Add a note for the future about texture latency calculation.Eric Anholt2016-11-291-0/+20
* vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.Eric Anholt2016-11-294-29/+37
* vc4: Restructure VPM write optimization into two passes.Eric Anholt2016-11-291-18/+10
* vc4: Make qir_for_each_inst_inorder() safe against removal.Eric Anholt2016-11-291-1/+1
* vc4: Split optimizing VPM writes from VPM reads.Eric Anholt2016-11-295-51/+110
* vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt2016-11-299-89/+194
* vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt2016-11-2917-36/+34
* vc4: Replace the qinst src[] with a fixed-size array.Eric Anholt2016-11-293-4/+2
* vc4: Remove qir_inst4().Eric Anholt2016-11-292-25/+0
* swr: [rasterizer memory] only clear up to the LOD sizeIlia Mirkin2016-11-281-2/+8
* swr: [rasterizer memory] hook up stencil clears for ClearTileIlia Mirkin2016-11-281-5/+8
* swr: [rasterizer memory] add support for clearing Z32F_X32 and Z16Ilia Mirkin2016-11-281-0/+2
* swr: don't clear all dirty bits when changing so targetsIlia Mirkin2016-11-281-1/+1
* swr: [rasterizer core] fix typo in scissor tile-alignment logicIlia Mirkin2016-11-281-1/+1
* st/omx/dec/h264: consider POC as signed instead of unsignedChandu Babu Namburu2016-11-281-3/+3
* freedreno: fix slice size for imported buffersRob Clark2016-11-271-0/+1
* freedreno/a3xx: make _emit_const() staticRob Clark2016-11-272-5/+1
* freedreno/a4xx: make _emit_const() staticRob Clark2016-11-273-6/+2
* gm107/ir: optimize 32-bit CONST load to movSamuel Pitoiset2016-11-262-0/+17
* gm107/ir: do not combine CONST loadsSamuel Pitoiset2016-11-261-2/+7
* clover: Restore support for LLVM <= 3.9.Vedran Miletić2016-11-242-6/+21
* scons: Recognize LLVM_CONFIG environment variable.Vinson Lee2016-11-241-1/+2
* util: fix memory leak from the fragment shaders for SINT<->UINT blitsCharmaine Lee2016-11-231-1/+1
* swr: clear every layer of the attached surfacesIlia Mirkin2016-11-231-6/+29
* swr: [rasterizer core] pipe renderTargetArrayIndex through to clearsIlia Mirkin2016-11-237-20/+35
* swr: [rasterizer core] clear data now comes in as floatIlia Mirkin2016-11-231-10/+4
* swr: [rasterizer core] actually perform clear before store in GetHotTileIlia Mirkin2016-11-231-0/+12
* radeonsi: print new opt flags in si_dump_shader_keyMarek Olšák2016-11-231-0/+9
* radeonsi: add a debug flag that disables optimized shader variantsMarek Olšák2016-11-233-0/+7
* swr: [rasterizer core] fix cast for stencil clear valueTim Rowley2016-11-221-3/+2
* swr: color interpolation is also supposed to get perspective divisionIlia Mirkin2016-11-221-2/+4
* swr: add sprite coord enable mask to fs keyIlia Mirkin2016-11-222-1/+3
* swr: rework vert <-> frag shader linkage logicIlia Mirkin2016-11-221-43/+50
* swr: flatshading makes color outputs flat, it doesn't affect othersIlia Mirkin2016-11-221-4/+2
* swr: only broadcast color0 value, not all color valuesIlia Mirkin2016-11-221-1/+2
* swr: report a reasonable max lod biasIlia Mirkin2016-11-221-1/+1
* swr: avoid using exceptions for expected condition handlingIlia Mirkin2016-11-221-5/+4
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