| Commit message (Collapse) | Author | Age | Files | Lines |
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use MUL+MAD+MOV instead.
Reviewed-by: Roland Scheidegger <[email protected]>
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use DP4 or DP3 + ADD.
Reviewed-by: Roland Scheidegger <[email protected]>
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use DP3 instead.
Reviewed-by: Roland Scheidegger <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
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use MEMBAR instead
Reviewed-by: Roland Scheidegger <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
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clip_regs aren't marked dirty when writes_viewport_index is changed.
Cc: 17.2 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Now we can finally stop flushing L2 data.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Vulkan doesn't do it anymore.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want.
Reviewed-by: Nicolai Hähnle <[email protected]>
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- don't precompile LS and ES (they don't exist on GFX9), compile as VS instead
- don't precompile HS and GS (we don't have LS and ES parts)
Reviewed-by: Nicolai Hähnle <[email protected]>
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Cc: 17.2 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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We have come to the conclusion that it doesn't improve performance.
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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The workaround will do for now. The root cause is still unknown.
This fixes new piglit: 16in-1out
Cc: 17.1 17.2 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Currently, when the array is full it is resized but it can grow
over and over because we don't try to re-use descriptor slots.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Using VRAM address as bindless handles is not a good idea because
we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
because it has no information about the pointer.
Instead, use slots indexes like the existing descriptors. Note
that we use fixed 16-dword slots for both samplers and images.
This doesn't really matter because no real apps use image handles.
This improves performance with DOW3 by +7%.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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To share common code between rw buffers and bindless descriptors.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Looks like it's useless to initialize that field when CE is
unused. This will also allow to declare more than 64 elements
for the array of bindless descriptors.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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The number of bindless descriptors is dynamic and we definitely
have to support more than 256 slots.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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A new pair of user SGPR is needed for loading the bindless
descriptors from shaders. Because the descriptors are global for
all stages, there is no need to add separate indices for GFX9.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Will be used for allocating bindless descriptor slots for
RadeonSI.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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It is no longer used.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Also add missing trace emits and CS logging for compute launches.
Reviewed-by: Marek Olšák <[email protected]>
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Use the auto logger facility, so that CS chunks will be interleaved
with other log info.
v2:
- fix some crashes when not using CE
- fix skipping "previous" chunks of current (unflushed) IB
- fix error handling in si_begin_cs_debug
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Keep together the parts that won't use the deferred logging mechanism.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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To allow keep-alive for deferred logging.
Reviewed-by: Marek Olšák <[email protected]>
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We'll add radeonsi-specific code to set_log_context in later patches,
but we may want to log from common code. Hence keep the log pointer
in r600_common_context.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and
then allocates user pointers aligned to that value for its tests.
The minimum value is defined as:
the size (in bits) of the largest OpenCL built-in data type supported
by the device (long16 in FULL profile, long16 or int16 in EMBEDDED
profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM.
At the moment, all known devices that support user pointers require
CPU page alignment for buffers created from user pointers, so just
query that from sysconf.
v3: Use std::max instead of MAX2 (Francisco)
Add missing unistd include
v2: Use system page size instead of a new pipe cap
Signed-off-by: Aaron Watry <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by (v2): Jan Vesely <[email protected]>
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No Piglit regressions.
Reviewed-by: Charmaine Lee <[email protected]>
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Trivial.
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Trivial.
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