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* r600: add SET_NULL_SHADER macro.Dave Airlie2015-12-071-2/+7
* r600: move clip misc and streamout stream updates to a single placeDave Airlie2015-12-071-6/+11
* r600: move selecting shaders into earlier code.Dave Airlie2015-12-071-5/+4
* r600: use a macro to remove common shader selection code.Dave Airlie2015-12-071-12/+9
* r600: move to using hw stages array for hw stage atomsDave Airlie2015-12-075-32/+24
* r600: make adjust_gprs use hw stages.Dave Airlie2015-12-072-55/+64
* r600: introduce HW shader stage definesDave Airlie2015-12-071-0/+11
* r600: fix masks for two of the unused evergreen regs.Dave Airlie2015-12-071-2/+2
* gallium: Remove redundant NULL ptr checksEdward O'Callaghan2015-12-062-8/+5
* gallium/drivers: Sanitize NULL checks into canonical formEdward O'Callaghan2015-12-0654-132/+132
* gallium/auxiliary: Sanitize NULL checks into canonical formEdward O'Callaghan2015-12-0641-61/+61
* gallium/auxiliary: Trivial code style cleanupEdward O'Callaghan2015-12-0625-91/+91
* gallium/drivers: Trivial code-style cleanupEdward O'Callaghan2015-12-0616-58/+58
* gallium/auxiliary: Fix zero integer literal to pointer comparisonEdward O'Callaghan2015-12-061-1/+1
* winsys/amdgpu: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-061-4/+2
* svga: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-062-2/+2
* llvmpipe: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-062-4/+4
* gallium/drivers/nouveau: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-0614-22/+20
* gallium/radeon*: Remove useless castsEdward O'Callaghan2015-12-065-14/+11
* nv50/ir: fold shl + mul with immediatesIlia Mirkin2015-12-051-0/+16
* nv50/ir: propagate indirect loads into instructionsIlia Mirkin2015-12-051-0/+52
* nv50/ir: flip shl(add, imm) into add(shl, imm)Ilia Mirkin2015-12-051-4/+34
* vc4: Fix accidental scissoring when scissor is disabled.Eric Anholt2015-12-051-5/+23
* vc4: Disable RCL blitting when scissors are enabled.Eric Anholt2015-12-051-0/+3
* vc4: Bring over cleanups from submitting to the kernel.Eric Anholt2015-12-054-87/+78
* nvc0: expose a group of performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-2/+8
* nvc0: re-introduce performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-5/+188
* nvc0: remove useless counting operations for MP countersSamuel Pitoiset2015-12-051-101/+5
* nvc0: remove old performance metrics support on KeplerSamuel Pitoiset2015-12-052-37/+0
* nvc0: remove wrong inst_issued HW SM perf counter on KeplerSamuel Pitoiset2015-12-052-3/+0
* nvc0: add missing HW SM perf counters for SM30 (Kepler)Samuel Pitoiset2015-12-053-0/+10
* nvc0: fix the comment that describe MP counters storage on KeplerSamuel Pitoiset2015-12-051-0/+5
* freedreno/ir3: nir shader prints with 'disasm' debug optionRob Clark2015-12-051-2/+2
* gallium/util: fix pipe_debug_message macro to allow 0 argsIlia Mirkin2015-12-041-1/+1
* vc4: Add debug dumping of MSAA surfaces.Eric Anholt2015-12-042-6/+145
* vc4: Add support for laying out MSAA resources.Eric Anholt2015-12-041-5/+20
* vc4: Add support for storing sample mask.Eric Anholt2015-12-045-0/+24
* vc4: Fix up tile alignment checks for blitting using just an RCL.Eric Anholt2015-12-041-6/+22
* vc4: Add support for loading sample mask.Eric Anholt2015-12-046-1/+19
* freedreno/ir3: convert scheduler back to recursive algoRob Clark2015-12-042-127/+204
* freedreno/ir3: don't reuse a0.x across blocksRob Clark2015-12-041-7/+14
* freedreno/ir3: rename ir3_block::bdRob Clark2015-12-043-11/+11
* xvmc: force assertion in XvMC testsGiuseppe Bilotta2015-12-045-0/+10
* nv50/ir: replace zeros in movs as wellIlia Mirkin2015-12-031-2/+1
* nv50/ir: fold fma/mad when all 3 args are immediatesIlia Mirkin2015-12-031-0/+30
* nv50/ir: avoid looking at uninitialized srcMods entriesIlia Mirkin2015-12-032-2/+2
* nv50/ir: fix DCE to not generate 96-bit loadsIlia Mirkin2015-12-031-1/+31
* draw: fix clipping of layer/vp index outputsRoland Scheidegger2015-12-041-139/+186
* softpipe: use provoking vertex for layerRoland Scheidegger2015-12-041-2/+2
* llvmpipe: use provoking vertex for layer/viewportRoland Scheidegger2015-12-042-17/+32
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