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* tgsi: Add support for global / private / input MEMORYHans de Goede2016-03-217-25/+50
| | | | | | | | | | | | | | | | Extend the MEMORY file support to differentiate between global, private and shared memory, as well as "input" memory. "MEMORY[x], INPUT" is intended to access OpenCL kernel parameters, a special memory type is added for this, since the actual storage of these (e.g. UBO-s) may differ per implementation. The uploading of kernel parameters is handled by launch_grid, "MEMORY[x], INPUT" allows drivers to use an access mechanism for parameter reads which matches with the upload method. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (v1) Reviewed-by: Samuel Pitoiset <[email protected]> (v2)
* tgsi: Fix decl.Atomic and .Shared not propagating when parsing tgsi textHans de Goede2016-03-211-0/+6
| | | | | | | | | When support for decl.Atomic and .Shared was added, tgsi_build_declaration was not updated to propagate these properly. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (v1) Reviewed-by: Samuel Pitoiset <[email protected]> (v2)
* tgsi: Fix return of uninitialized memory in tgsi_*_instruction_memoryHans de Goede2016-03-201-0/+4
| | | | | | | | | | | | | tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory") Cc: Nicolai Hähnle <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/omx/dec: Correct the timestampingNishanth Peethambaran2016-03-204-8/+34
| | | | | | | | | Attach the timestamp to the dpb buffer and use that timestamp while pushing buffer from dpb list to the omx client. Reviewed-by: Christian König <[email protected]> Signed-off-by: Nishanth Peethambaran <[email protected]> Cc: "11.1 11.2" <[email protected]>
* st/omx: Remove trailing spacesNishanth Peethambaran2016-03-203-31/+31
| | | | | | Reviewed-by: Christian König <[email protected]> Signed-off-by: Nishanth Peethambaran <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nv50/ir: fix indirect texturing for non-array textures on nvc0Ilia Mirkin2016-03-201-3/+7
| | | | | | | | | | | | | | | | | | | If a layer parameter is provided, we want to flip it to position 0 (and combine it with any indirect params). However if the target is not an array, there is no layer, so we have to shift all of the arguments down by one to make room for it. This fixes situations where there were non-coordinate parameters, such as bias, lod, depth compare, explicit derivatives. Instead of adding a new parameter at the front for the indirect reference, we would swap one of those in its place. Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.compute.*shadow Signed-off-by: Ilia Mirkin <[email protected]> Reported-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nv50/ir: normalize cube coordinates after derivatives have been computedIlia Mirkin2016-03-204-15/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In "manual" derivative mode (always used on nv50 and sometimes on nvc0 but always for cube), the idea is that using the quadop instruction, we set up the "other" quads to have values such that the derivatives work out, and then run the texture instruction as if nothing were strange. It pulls values from the other lanes, and does its magic. However cube coordinates have to be normalized - one of the 3 coords has to be 1, to determine which is the major axis, to say which face is being sampled. We were normalizing the coordinates first, and then adding the derivatives. This is wrong for two reasons: - the coordinates got normalized by a scaling factor but the derivatives didn't - the result of the addition didn't end up normalized To resolve this, we flip the logic around to normalize *after* the per-lane coordinates are set up. This fixes a bunch of textureGrad cube dEQP tests. NOTE: nv50 cube arrays with explicit derivatives are still broken, to be resolved at a later date. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* gallium/radeon: remove remnants of R600 TGSI->LLVMMarek Olšák2016-03-202-20/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: flatten if (1) statement after removal of TGSI->LLVMMarek Olšák2016-03-201-81/+79
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: remove TGSI->LLVM translationMarek Olšák2016-03-209-1107/+89
| | | | | | | | | | It was useful for testing and as a prototype for radeonsi bringup, but it's not used anymore and doesn't support OpenGL 3.3 even. v2: try to fix OpenCL build Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Jan Vesely <[email protected]>
* gallium/radeon: remove old CS tracingMarek Olšák2016-03-2020-476/+23
| | | | | | | | | | | | | | Cons: - it was only integrated in r600g - it doesn't work with GPUVM - it records buffer contents at the end of IBs instead of at the beginning, so the replay isn't exact - it lacks an IB parser and user-friendliness A better solution is apitrace in combination with gallium/ddebug, which has a complete IB parser and can pinpoint hanging CP packets. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: process TGSI property NEXT_SHADERMarek Olšák2016-03-192-3/+33
| | | | | | | | | | | | This allows compiling the main shader part as ES or LS. If we get the correct hint, non-separable GLSL shaders no longer have to be compiled as VS first, followed by LS or ES compiled on demand. The result is that fewer shaders are compiled by piglit, but it doesn't improve piglit running time. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add TGSI property NEXT_SHADERMarek Olšák2016-03-195-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | Radeonsi needs to know which shader stage will execute after a shader in order to make the best decision about which shader variant to compile first. This is only set for VS and TES, because we don't need it elsewhere. VS has 3 variants: - next shader is FS - next shader is GS - next shader is TCS TES has 2 variants: - next shader is FS - next shader is GS Currently, radeonsi always assumes the next shader is FS, which is suboptimal, since st/mesa always knows which shader is next if the GLSL program is not a "separate shader". By default, ureg always sets "next shader is FS". Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0/ir: Use double constant in handleSQRTPierre Moreau2016-03-191-1/+1
| | | | | | Fixes: a100d89d0998 (nv50,nvc0: Fix invalid constant.) Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: force-enable derivatives on TXD opsIlia Mirkin2016-03-192-1/+4
| | | | | | | | | This matters especially in vertex shaders, where derivatives are disabled by default. This fixes textureGrad in vertex shaders on nv50. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nv50: reset TFB bufctx when we no longer hold a reference to the buffersIlia Mirkin2016-03-192-3/+3
| | | | | | | | | | | | | This fix is analogous to commit ff085d014. This fixes some use-after-free situations in dEQP when an xfb state is removed, and then a clear is triggered, which only does a partial validation. It would attempt to read the no-longer-valid buffers, resulting in crashes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nvc0: avoid using magic numbers for the uniform_bo offsetsSamuel Pitoiset2016-03-198-44/+73
| | | | | | | | | | | | | | | Instead make use of constants to improve readability. The first 32 bytes of the driver constant buffer are unknown... This doesn't seem to be used in the codegen part, but if the texBindBase offset is shifted from 0x20 to 0x00, this breaks the universe for really weird reasons. This sounds like to be related to textures. Anyway, name this NVC0_CB_AUX_UNK_INFO and add a todo should be enough for now. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nv50/ir: make use of auxCBSlot instead of magic numbersSamuel Pitoiset2016-03-192-2/+4
| | | | | | | | | | | | | This avoids using magic numbers for the driver constbuf slot which is always 15 except for compute shaders on gk104+ where the slot 0 is used. For gk104+, some special compute-related values like the thread index are uploaded to screen->parm which is currently bound on c0. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Acked-by: Pierre Moreau <[email protected]>
* nv50,nvc0: replace resInfoCBSlot by auxCBSlotSamuel Pitoiset2016-03-196-16/+10
| | | | | | | | | Having two different variables for the driver constant buffer slot is confusing and really useless. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Acked-by: Pierre Moreau <[email protected]>
* nv50/ir: fix compilation warning in handleSharedATOM()Samuel Pitoiset2016-03-191-0/+1
| | | | | | | | In release build mode only, op may be used uninitialized because the assertion has been removed. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: Fix invalid constant.Vinson Lee2016-03-181-1/+1
| | | | | | | | | | | | | Fix clang build error. CXX codegen/nv50_ir_lowering_nvc0.lo codegen/nv50_ir_lowering_nvc0.cpp:1783:42: error: invalid suffix 'd' on floating constant Value *zero = bld.loadImm(NULL, 0.0d); ^ Fixes: c1e4a6bfbf01 ("nv50,nvc0: handle SQRT lowering inside the driver") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: Mark compute states as dirty on context switchPierre Moreau2016-03-191-0/+1
| | | | | | Signed-off-by: Pierre Moreau <[email protected]> [ Samuel Pitoiset: Trivial rebase conflict ] Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: print SUBFM subopsSamuel Pitoiset2016-03-191-0/+9
| | | | | | | Only 3d subop is currently emitted. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: add a new validation path for computeSamuel Pitoiset2016-03-191-12/+13
| | | | | | | | | This makes use of the new state validation interface to be consistent with 3d. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rework nv50_compute_validate_program()Samuel Pitoiset2016-03-193-31/+17
| | | | | | | | | | | Reduce the amount of duplicated code by re-using nv50_program_validate(). While we are at it, change the prototype to return void. We don't check anymore if the translation fails but improving the state validation is a long process. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rework the validation path for 3DSamuel Pitoiset2016-03-194-16/+36
| | | | | | | | | This exposes an interface for state validation that will be also used to rework the compute validation path. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rename 3d binding points to NV50_BIND_3D_XXXSamuel Pitoiset2016-03-198-46/+46
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rename 3d dirty flags to NV50_NEW_3D_XXXSamuel Pitoiset2016-03-198-112/+112
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rename NV50_COMPUTE to NV50_CPSamuel Pitoiset2016-03-193-52/+52
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* nv50: rename nv50_context::dirty to nv50_context::dirty_3dSamuel Pitoiset2016-03-198-57/+57
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Tested-by: Pierre Moreau <[email protected]>
* tgsi: add tgsi_transform_op3_inst() functionBrian Paul2016-03-181-0/+34
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* gallium/swr: Cleaned up some context-resource managementGeorge Kyriazis2016-03-175-26/+27
| | | | | | | | | | Removed bound_to_context. We now pick up the context from the screen instead of the resource itself. The resource could be out-of-date and point to a pipe that is already freed. Fixes manywin mesa xdemo. Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: fix Hyper-Z hangs on P2 configsMarek Olšák2016-03-171-2/+8
| | | | | Cc: 11.1 11.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r300g: add missing layer argument to rws->buffer_get_handle() callBrian Paul2016-03-171-1/+1
| | | | | | Fixes compilation error since 5aea0d691. Reviewed-by: Christian König <[email protected]>
* radeon/winsys: add layer support for BO exportChristian König2016-03-174-0/+7
| | | | | | | Add layer support to export individual array layers. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/winsys: add offset support for BO import/exportChristian König2016-03-175-18/+33
| | | | | | | Add offset support to handle NV12 offsets as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/winsys/drm: add layer to struct winsys_handleChristian König2016-03-171-0/+5
| | | | | | | For exporting a specific layer of an array texture. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/winsys/drm: add offset to struct winsys_handleChristian König2016-03-176-0/+13
| | | | | | | We are going to need this for EGL_EXT_image_dma_buf_import. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-176-15/+15
| | | | | | | | | | | | | | | | | | | | | | v2: Squash multiple commits addressing the new parameter in different files so we don't break the build (Iago) v3: Fix tgsi (Samuel) v4: Fix nir_clone.c (Samuel) v5: Fix vc4 and freedreno (Iago) v6 (Sam) - Fix build errors in nir_lower_indirect_derefs - Use helper to get type size from nir_alu_type. Signed-off-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Tested-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-174-14/+14
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some opcodes need explicit bitsizes, and sometimes we need to use the double version when constant folding. v2: fix output type for u2f (Iago) v3: do not change vecN opcodes to be float. The next commit will add infrastructure to enable 64-bit integer constant folding so this is isn't really necessary. Also, that created problems with source modifiers in some cases (Iago) v4 (Jason): - do not change bcsel to work in terms of floats - leave ldexp generic Squashed changes to handle different bit sizes when constant folding since otherwise we would break the build. v2: - Use the bit-size information from the opcode information if defined (Iago) - Use helpers to get type size and base type of nir_alu_type enum (Sam) - Do not fallback to sized types to guess bit-size information. (Jason) Squashed changes in i965 and gallium/nir drivers to support sized types. These functions should only see sized types, but we can't make that change until we make sure that nir uses the sized versions in all the relevant places. A later commit will address this. Signed-off-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* vc4: Move discard handling to the condition flag.Eric Anholt2016-03-165-34/+29
| | | | | | | | | | | | | | | Now that the field exists in the instruction, we can make discards less special. As a bonus, that means that we should be able to merge some more .sf instructions together when we get around to that. This causes some scheduling changes, as it allows tlb_color_reads to be delayed past the discard condition setup. Since the tlb_color_read ends up later, this may mean performance improvements, but I haven't tested. total instructions in shared programs: 78114 -> 78035 (-0.10%) instructions in affected programs: 1922 -> 1843 (-4.11%) total estimated cycles in shared programs: 234318 -> 234329 (0.00%) estimated cycles in affected programs: 8200 -> 8211 (0.13%)
* vc4: Don't make a temporary for setting flags.Eric Anholt2016-03-161-1/+2
| | | | | | | | | The register allocator doesn't really do anything about the temp, so it doesn't seem like it should matter. However, the scheduler would think that a new def is being created. This doesn't change anything yet, but it avoids a bunch of regressions in the next commit.
* vc4: Add a safety check for setting flags.Eric Anholt2016-03-161-0/+3
| | | | | If a pack was on the src reg, should it be a float, int, or mul unpack? Just complain, instead.
* vc4: Reuse list_for_each_entry_safe_rev().Eric Anholt2016-03-161-6/+2
| | | | This didn't exist when I wrote the code.
* vc4: Coalesce instructions using VPM reads into the VPM read.Varad Gautam2016-03-153-7/+71
| | | | | | | | | | | | | | | This is done instead of copy propagating the VPM reads into the instructions using them, because VPM reads have to stay in order. shader-db results: total instructions in shared programs: 78509 -> 78114 (-0.50%) instructions in affected programs: 5203 -> 4808 (-7.59%) total estimated cycles in shared programs: 234670 -> 234318 (-0.15%) estimated cycles in affected programs: 5345 -> 4993 (-6.59%) Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Rhys Kidd <[email protected]>
* vc4: rename file to group vpm optimizations togetherVarad Gautam2016-03-152-2/+2
| | | | | | | | This file will contain optimization passes for both vpm reads and writes. Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Fix failures with nir_extract_* since the addition of the opcodes.Eric Anholt2016-03-151-0/+2
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* llvmpipe: fix lp_rast_plane alignment on 32bitRoland Scheidegger2016-03-152-0/+8
| | | | | | | | | | | | Some rasterization code relies (for sse) on the first and third planes (but not the second for now) being 128bit aligned, and we didn't get that on 32bit - I mistakenly thought the 64bit number in the struct would get the thing aligned to 64bit even on 32bit archs. Stephane Marchesin really figured this out. Reviewed-by: Jose Fonseca <[email protected]> CC: <[email protected]>
* draw: fix line stipplingRoland Scheidegger2016-03-151-15/+15
| | | | | | | | | | | | | | | | The logic was comparing actual ints, not true/false values. This meant that it was emitting always multiple line segments instead of just one even if the stipple test had the same result, which looks inefficient, and the segments also overlapped thus breaking line aa as well. (In practice, with the no-op default line stipple pattern, for a 10-pixel long line from 0-9 it was emitting 10 segments, with the individual segments ranging from 0-1, 0-2, 0-3 and so on.) This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94193 Reviewed-by: Jose Fonseca <[email protected]> CC: <[email protected]>
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