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* gallium/radeon: ignore the level parameter in buffer_transfer_mapMarek Olšák2017-02-101-5/+4
* gallium/radeon: fix performance of buffer readbacksMarek Olšák2017-02-101-8/+9
* radeonsi: align vertex buffer descriptor list size for optimal prefetchMarek Olšák2017-02-104-2/+7
* radeonsi: align shader binaries to CP DMA alignment for optimal prefetchMarek Olšák2017-02-101-1/+2
* radeonsi: move CP_DMA_ALIGNMENT definitionMarek Olšák2017-02-102-10/+10
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-103-6/+6
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-103-17/+8
* radeonsi: reduce the number of FMASK input coordinatesMarek Olšák2017-02-101-7/+3
* radeonsi: write shader asm annotated with wave info into GPU hang reportsMarek Olšák2017-02-103-3/+252
* radeonsi: write wave information into GPU hang reportsMarek Olšák2017-02-101-0/+20
* tgsi-dump: dump label if instruction has oneMarc-André Lureau2017-02-101-11/+13
* tgsi: remove ureg_label_insnMarc-André Lureau2017-02-102-38/+0
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nv50/ir: always return 0 when trying to read thread id along unit dimIlia Mirkin2017-02-094-5/+17
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0: increase number of ubo binding pointsIlia Mirkin2017-02-091-3/+2
* nvc0: expose int64Ilia Mirkin2017-02-091-1/+1
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-096-5/+302
* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-0917-0/+18
* swr: [rasterizer jitter] Pass LLVM-IR size into jitterTim Rowley2017-02-083-3/+4
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-293/+331
* swr: [rasterizer jitter] Disable unsafe FP optimizations in the jitterTim Rowley2017-02-081-1/+1
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-142/+243
* swr: [rasterizer jitter] Add DEBUGTRAP jit builder functionTim Rowley2017-02-082-1/+9
* swr: [rasterizer jitter] Multisample blend jit fixTim Rowley2017-02-081-2/+2
* swr: [rasterizer jitter] Change SimdVector representation to arrayTim Rowley2017-02-082-6/+2
* swr: [rasterizer jitter] Fix issues with stream-out on llvm>=3.8Tim Rowley2017-02-083-6/+6
* swr: [rasterizer jitter] Adjust jitter header includesTim Rowley2017-02-086-11/+11
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-085-43/+813
* r600/sb: Fix memory leakBartosz Tomczyk2017-02-081-1/+7
* gallium/tgsi: fix oob access in parse instructionLi Qiang2017-02-071-1/+1
* swr: [rasterizer core] Removed unused clip code.Bruce Cherniak2017-02-062-26/+0
* swr: [rasterizer core] Remove dead code Clipper::ClipScalar()Bruce Cherniak2017-02-061-39/+0
* gallium: Remove vc4 simulator hack from loader infrastructure.Eric Anholt2017-02-062-21/+0
* targets: Use a macro to reduce cut and paste in driver setup.Eric Anholt2017-02-061-111/+22
* radeon/ac: move common llvm build functions to a separate file.Dave Airlie2017-02-071-0/+1
* winsys/amdgpu: avoid potential segfault in amdgpu_bo_map()Samuel Pitoiset2017-02-031-7/+10
* ilo: EOL unmaintained older gallium intel driverEdward O'Callaghan2017-02-03120-58007/+0
* ilo: EOL drop unmaintained gallium drv from buildsysEdward O'Callaghan2017-02-037-35/+0
* ilo: EOL unplumb unmaintained gallium drv from winsysEdward O'Callaghan2017-02-035-85/+0
* radeonsi/ac: move most of emit_ddxy to shared code.Dave Airlie2017-02-031-71/+7
* radeonsi/ac: move get thread id to shared code.Dave Airlie2017-02-031-55/+2
* radeonsi/ac: move tbuffer store and buffer load to shared code.Dave Airlie2017-02-031-185/+40
* radeonsi/ac: move a bunch of load/store related things to common code.Dave Airlie2017-02-032-94/+27
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