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* radeon/uvd: add Define Restart Interval to MJPEG bitstream reconstructionLeo Liu2017-09-021-0/+11
* radeon/uvd: fix MJPEG quantization table indexLeo Liu2017-09-021-1/+1
* freedreno: skip batch-cache for compute shadersRob Clark2017-09-021-7/+1
* swr: Report format max_samples=1 to maintain support for "fake" msaa.Cherniak, Bruce2017-09-011-11/+11
* radeonsi: move si_vm_fault_occured() to AMD common codeSamuel Pitoiset2017-09-011-102/+4
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nvc0: write 0 to pipeline_statistics.cs_invocationsKarol Herbst2017-08-311-0/+1
* llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 loadBen Crocker2017-09-011-2/+28
* gallivm: correct channel shift logic on big endianRay Strode2017-09-011-1/+7
* winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2Christian König2017-08-313-5/+27
* radeonsi: set a per-buffer flag that disables inter-process sharing (v4)Marek Olšák2017-08-314-28/+56
* svga: include sample count in surface_size() computationBrian Paul2017-08-301-1/+1
* winsys/amdgpu: add BO to the global list only when RADEON_ALL_BOS is setSamuel Pitoiset2017-08-304-11/+17
* radeonsi: update dirty_level_mask before dispatchingSamuel Pitoiset2017-08-302-0/+6
* llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSORBrian Paul2017-08-291-0/+6
* ac/debug: Support multiple trace ids for nested IBs.Bas Nieuwenhuizen2017-08-291-9/+10
* radeonsi: stop leaking nirTimothy Arceri2017-08-291-0/+1
* radeonsi: rewrite late alloc VS limit computationMarek Olšák2017-08-281-12/+25
* gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmationMarek Olšák2017-08-281-3/+9
* gallium/u_threaded: rename IGNORE_VALID_RANGE -> NO_INFER_UNSYNCHRONIZEDMarek Olšák2017-08-283-5/+5
* gallium/u_threaded: disallow discard_range if map_buffer is unsynchronizedMarek Olšák2017-08-281-1/+3
* radeonsi: correct maximum wave count per SIMDMarek Olšák2017-08-281-1/+12
* gallium/docs: Fix an inequality sign of TGSI_SEMANTIC_SUBGROUP_LT_MASKGwan-gyeong Mun2017-08-281-1/+1
* gallium/docs: fix a typoGwan-gyeong Mun2017-08-281-1/+1
* i915g: Remove a few unused variablesEduardo Lima Mitev2017-08-281-16/+0
* Revert "radeonsi: get the raster config from AMDGPU on SI"Marek Olšák2017-08-271-17/+0
* etnaviv: use correct param for etna_compatible_rs_format(..)Christian Gmeiner2017-08-261-1/+1
* gallium/vbuf: fix buffer reference bugsBrian Paul2017-08-251-4/+3
* gallium/u_threaded: fix a typoMarek Olšák2017-08-251-1/+1
* a2xx: fix DST_ALPHA blending for non-alpha formatsIlia Mirkin2017-08-253-5/+21
* a2xx: set constant blend colorIlia Mirkin2017-08-251-0/+9
* radeonsi: set IF_THRESHOLD to 4Timothy Arceri2017-08-251-1/+1
* glsl: pass shader source keys to the disk cacheTimothy Arceri2017-08-251-1/+1
* radeonsi: get the raster config from AMDGPU on SIMarek Olšák2017-08-241-0/+17
* radeonsi: clean up setting GRBM_GFX_INDEXMarek Olšák2017-08-241-19/+22
* radeonsi: move PA_SC_RASTER_CONFIG emission into a separate functionMarek Olšák2017-08-241-70/+73
* gallivm: remove unused variableBrian Paul2017-08-241-2/+0
* pipe-loader: use MAYBE_UNUSED to silence warningBrian Paul2017-08-241-1/+2
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
* st/va: exclude the buffer reallocation for encode caseLeo Liu2017-08-231-1/+1
* swr: limit pipe_draw_info->restart_index usageTim Rowley2017-08-231-1/+4
* radeonsi: fix wrong assertion in si_init_bindless_descriptors()Samuel Pitoiset2017-08-231-1/+1
* radeon/video: Return false explicitly for HEVC if not the caseLeo Liu2017-08-231-0/+1
* gallium/docs: Fix the math formula of U2I64Gwan-gyeong Mun2017-08-231-2/+2
* gallium/docs: Add missing word "Not"Gwan-gyeong Mun2017-08-231-1/+1
* tgsi: store opcode mnemonics in a separate tableNicolai Hähnle2017-08-232-6/+16
* gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonicNicolai Hähnle2017-08-235-7/+10
* tgsi: macro-ify the opcodes tableNicolai Hähnle2017-08-233-251/+263
* tgsi: remove post_indent from some 64-bit opcodesNicolai Hähnle2017-08-231-6/+6
* tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bitNicolai Hähnle2017-08-231-2/+2
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