summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Collapse)AuthorAgeFilesLines
* svga: pass context to svga_tgsi_vgpu9_translate()Brian Paul2015-10-164-4/+8
| | | | | | Will be used for upcoming change. Reviewed-by: Charmaine Lee <[email protected]>
* svga: remove svga_tgsi_vgpu9_translate() call in GS pathBrian Paul2015-10-161-7/+3
| | | | | | We can never have geometry shaders with vgpu9. Reviewed-by: Charmaine Lee <[email protected]>
* freedreno: add debug option to dirty state after drawRob Clark2015-10-153-2/+7
| | | | | | Similar to "dclear", "ddraw" will mark all state dirty after each draw. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: cache-flush is needed after MEM_WRITERob Clark2015-10-153-5/+14
| | | | | | | | Otherwise the mem2gmem blit would see potentially bogus texture coordinates. Fixes an issue that shows up with glamor. CC: "11.0" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* gallium/util: fix debug_get_flags_option on 32-bit harderRob Clark2015-10-151-3/+3
| | | | | | | | (yes, we want PRI?64, but we want the x version rather than the u version) Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv30: include the header of ffs prototypeChih-Wei Huang2015-10-151-0/+1
| | | | | | | | It fixes a building error of the android 6.0 64-bit target. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
| | | | | | | | Note Android version before Lollipop is not supported. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* r600/vce: enable VCE for trinity/richlandChristian König2015-10-131-1/+21
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600/uvd: disable UVD tiling by defaultChristian König2015-10-131-3/+5
| | | | | | | It has only minimal advantages for post processing and doesn't work with VCE. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: Enable GL_ARB_gpu_shader5 extensionGlenn Kennard2015-10-131-1/+1
| | | | | Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: SB support for UBO indexingGlenn Kennard2015-10-1311-27/+140
| | | | | Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Support gs5 sampler indexing (v2)Glenn Kennard2015-10-139-25/+195
| | | | | | | [airlied: v2 cayman fixups] Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
| | | | | | | | | | | The act of ensuring that there is space can cause a flush to happen, which will emit the current screen fence. If that is the fence we're trying to wait on, then it will have been emitted as a result of doing the PUSH_SPACE. Don't attempt to emit it a second time. Signed-off-by: Ilia Mirkin <[email protected]> Fixes: 8053c9208f (nouveau: avoid emitting new fences unnecessarily) Cc: [email protected]
* u_vbuf: fix vb slot assignment for translated buffersNicolai Hähnle2015-10-121-0/+1
| | | | | | | | | | | Vertex attributes of different categories (constant/per-instance/ per-vertex) go into different buffers for translation, and this is now properly reflected in the vertex buffers passed to the driver. Fixes e.g. piglit's point-vertex-id divisor test. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* ilo: improve Gen8 defines based on its PRMsChia-I Wu2015-10-1213-121/+399
|
* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
| | | | | | | | | | | | We still have to push everything out, might as well kick earlier and flip pushbufs when we know we'll need it. This resolves some issues with the new policy of making sure that we always leave a bit of room at the end for fences. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: [email protected]
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
| | | | | | | | | | | | | | | | | | | | Right now we emit on every kick, but this is only necessary if something will ever be able to observe that the fence completed. If there are no refs, leave the fence alone and emit it another day. This also happens to work around an issue for the kick handler -- a kick can be a result of e.g. nouveau_bo_wait or explicit kick, or it can be due to lack of space in the pushbuf. We want the emit to happen in the current batch, so we want there to always be enough space. However an explicit kick could take the reserved space for the implicitly-triggered kick's fence emission if it happened right after. With the new mechanism, hopefully there's no way to cause two fences to be emitted into the same reserved space. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: [email protected]
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
| | | | | | | | | | In theory, GF110+ should also support NVC8_COMPUTE_CLASS but, in practice, a ILLEGAL_CLASS dmesg fail appears when using it. This fixes compute support and MP performance counters on GF110. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* tgsi: (trivial) kill c99-ism.Roland Scheidegger2015-10-091-2/+3
|
* tgsi/scan: add info about declared samplers (v2)Marek Olšák2015-10-092-0/+3
| | | | v2: get it from declarations, not instructions
* tgsi: add a utility for emulating some GL featuresMarek Olšák2015-10-093-0/+208
| | | | | | | | st/mesa will use this, but drivers can use it too. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* glsl: move shader_enums into nirRob Clark2015-10-094-3/+3
| | | | | | | | | | | | | | | | | | | | First step towards inverting the dependency between glsl and nir (so nir can be used without glsl). Also solves this issue with 'make distclean' Making distclean in mesa make[2]: Entering directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa' Makefile:2486: ../glsl/.deps/shader_enums.Plo: No such file or directory make[2]: *** No rule to make target '../glsl/.deps/shader_enums.Plo'. Stop. make[2]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa' Makefile:684: recipe for target 'distclean-recursive' failed make[1]: *** [distclean-recursive] Error 1 make[1]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src' Makefile:615: recipe for target 'distclean-recursive' failed make: *** [distclean-recursive] Error 1 Reported-by: Andy Furniss <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* nvc0: move HW SM queries to nvc0_query_hw_sm.c/h filesSamuel Pitoiset2015-10-098-796/+908
| | | | | | | Global performance counters (PCOUNTER) will be added to nvc0_query_hw_pm.c/h files. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move HW queries to nvc0_query_hw.c/h filesSamuel Pitoiset2015-10-098-1215/+1310
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move SW queries to nvc0_query_sw.c/h filesSamuel Pitoiset2015-10-095-84/+204
| | | | | | Loosely based on freedreno driver. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move nvc0_so_target_save_offset() to its correct locationSamuel Pitoiset2015-10-093-24/+19
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: add a header file for nvc0_querySamuel Pitoiset2015-10-097-189/+202
| | | | | | | | This will allow to split SW and HW queries in an upcoming patch. While we are at it, make use of nvc0_query struct instead of pipe_query. Signed-off-by: Samuel Pitoiset <[email protected]>
* gallium/ddebug: add missing dd_util.h to sources listEmil Velikov2015-10-081-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallium/ddebug: automake: sort sources alphabeticallyEmil Velikov2015-10-081-2/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: fix a GS hang on VIMarek Olšák2015-10-072-0/+19
| | | | | | | Broken by one of the cleanups: 0d46c3bc9d09b376d74f7399e1a2d1b0a923640b Not applicable to stable. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: remove TC L2 cache flush for index buffers on VIMarek Olšák2015-10-071-3/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* svga: whitespace fixes in svga_sampler_view.cBrian Paul2015-10-071-8/+16
|
* svga: whitespace fixes in svga_resource_buffer.cBrian Paul2015-10-071-26/+27
|
* svga: round UBO constant buffer size up/down to multiple of 16 bytesBrian Paul2015-10-071-0/+18
| | | | | | | | | | | | | | The svga3d device requires constant buffers to be a multiple of 16 bytes in size. OpenGL UBOs may not fit that restriction. As a work-around, round the size up if possible, else round down. Note that this patch only effects UBO constant buffers (index 1 or higher), not the 0th/default constant buffer. Fixes the game Grim Fandango Remastered. VMware bug 1510130. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
| | | | | | | | | | | | I started seeing a lot of situations on nv30 where fence emission wouldn't fit into the previous buffer (causing assertions). This ensures that whenever checking for space, we always leave a bit of extra room for the fence emission commands. Adjusts the nv30 and nvc0 fence emission logic to bypass the space checking as well. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]>
* vc4: use nir two-sided-color loweringBoyan Ding2015-10-062-24/+2
| | | | | | | | Similar to 9ffc1049ca (freedreno/ir3: use nir two-sided-color lowering). No piglit regression. Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Fix a leak of the last color read/write surface on context destroy.Eric Anholt2015-10-061-0/+3
|
* vc4: Fix a memory leak in the simulator case.Eric Anholt2015-10-061-1/+6
| | | | We validate per draw call, and need to free the shader per draw call, too.
* tgsi: add const qualifier to silence warningBrian Paul2015-10-061-1/+1
| | | | Trivial.
* nv30: always go through translate module on big-endianIlia Mirkin2015-10-041-0/+4
| | | | | | | | | | It seems like things are either coming in slighly wrong, or perhaps uploaded incorrectly, but either way passing them through the translate module seems to fix everything. Eventually we should figure out what's going wrong and fix it "for real", but this should do for now. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv30: pretend to have packed texture/surface formatsIlia Mirkin2015-10-041-12/+12
| | | | | | | | | This puts us in line with what the DDX/DRI2 st are expecting. It also happens to work... no idea why, but seems better to have it work than to ask lots of questions. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* st/dri: Use packed RGB formatsMichel Dänzer2015-10-042-17/+17
| | | | | | | | | | Fixes Gallium based DRI drivers failing to load on big endian hosts because they can't find any matching fbconfigs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789 Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
* radeonsi: enable PIPE_CAP_FORCE_PERSAMPLE_INTERPMarek Olšák2015-10-031-1/+1
| | | | | | Now st/mesa won't generate 2 variants for this state. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: do force_persample_interp in shaders for non-trivial casesMarek Olšák2015-10-033-19/+117
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement the simple case of force_persample_interpMarek Olšák2015-10-034-1/+37
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move SPI_PS_INPUT_ENA/ADDR registers to a separate stateMarek Olšák2015-10-034-14/+29
| | | | | | | This will be a derived state used for changing center->sample and centroid->sample at runtime. Reviewed-by: Michel Dänzer <[email protected]>
* tgsi/scan: add interpolation info into tgsi_shader_infoMarek Olšák2015-10-032-3/+101
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add per-sample interpolation control into rasterizer statOAeMarek Olšák2015-10-0316-0/+24
| | | | | | | | Required by ARB_sample_shading for drivers that don't want a shader variant in st/mesa. Reviewed-by: Ilia Mirkin <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* st/dri: don't use _ctx in client_wait_syncMarek Olšák2015-10-031-2/+5
| | | | | | | | | Not needed and it can be NULL. v2: fix dri2_get_fence_from_cl_event - thanks Albert Cc: 10.6 11.0 <[email protected]> Reviewed-by: Albert Freeman <[email protected]>
* r600g: only do depth-only or stencil-only in-place decompressionMarek Olšák2015-10-034-12/+43
| | | | | | | instead of always doing both. Usually, only depth is needed, so stencil decompression is useless. Reviewed-by: Michel Dänzer <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 13:36:33 +0000