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* automake: rework VL dependency trackingEmil Velikov2014-11-268-3/+18
| | | | | | | | | | | | | | | Set a single VL_{CFLAG,LIBS} for xcb and friends, and let each target check for it's relevant library alone. Required as with follow up commits we'll build aux/vl into a separate module, which needs VL_CFLAGS Cleanup add a couple of explicit LIBDRM_LIBS linking, as aux/vl itself requires libdrm, despite that LIBDRM_{RADEON,NOUVEAU...} may provide it as well. v2: Rebase. Make sure st/xvmc programs work. Cc: Christian König <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* llvmpipe: (trivial) remove redundant util_cpu_detect() call in lp_test_mainRoland Scheidegger2014-11-251-2/+0
| | | | Already called earlier.
* llvmpipe: fix lp_test_arit denorm handlingRoland Scheidegger2014-11-251-1/+37
| | | | | | | | | | | | | | | | | | llvmpipe disables denorms on purpose (on x86/sse only), because denorms are generally neither required nor desired for graphic apis (and in case of d3d10, they are forbidden). However, this caused some arithmetic tests using denorms to fail on some systems, because the reference did not generate the same results anymore. (It did not fail on all systems - behavior of these math functions is sort of undefined when called with non-standard floating point mode, hence the result differing depending on implementation and in particular the sse capabilities.) So, for the reference, simply flush all (input/output) denorms manually to zero in this case. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=67672. Reviewed-by: Jose Fonseca <[email protected]>
* nouveau: Fix build after STR/BRA opcode dropping.Eric Anholt2014-11-241-2/+0
| | | | | I missed these while git grepping for users of the dead opcodes. Sigh, macros.
* gallium: Drop the unused CND opcode.Eric Anholt2014-11-2411-82/+5
| | | | | | Nothing in the tree generates it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop unused BRA opcode.Eric Anholt2014-11-2412-37/+5
| | | | | | Never generated, and implemented in only nvfx vertprog. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused SFL/STR opcodes.Eric Anholt2014-11-2413-150/+10
| | | | | | Nothing generated them. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused RFL opcode.Eric Anholt2014-11-2410-98/+5
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop unused X2D opcode.Eric Anholt2014-11-2410-77/+4
| | | | | | Nothing in the tree generates it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused ARA opcode.Eric Anholt2014-11-2410-28/+5
| | | | | | | | Nothing in the tree generated it. v2: Only drop ARA, not ARR as well. Reviewed-by: Jose Fonseca <[email protected]> (v2)
* gallium: Drop the unused RCC opcode.Eric Anholt2014-11-2411-47/+5
| | | | | | Nothing in the tree generated it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the NRM and NRM4 opcodes.Eric Anholt2014-11-2411-347/+10
| | | | | | | They weren't generated in tree, and as far as I know all hardware had to lower it to a DP, RSQ, MUL. Reviewed-by: Jose Fonseca <[email protected]>
* ilo: Drop the explicit intialization of gaps in TGSI opcodes.Eric Anholt2014-11-241-22/+6
| | | | | | | | | The nice thing about the good way of initializing arrays like this is that you don't need to initialize everything in order, or even everything at all. Taking advantage of that only needs a tiny fixup to deal with the default NULL value of the pointers. I haven't dropped the initialization of opcodes that exist and are unsupported.
* r300: Drop the "/* gap */" notes.Eric Anholt2014-11-241-3/+0
| | | | | This switch statement's code structure isn't dependent on the numbers of the opcodes at all.
* r600: Drop the "/* gap */" notes.Eric Anholt2014-11-241-19/+0
| | | | | | | These are obviously the gaps already, due to the bare numbers with unsupported implementations. This makes inserting new gaps less irritating.
* nine: Drop use of TGSI_OPCODE_CND.Jose Fonseca2014-11-241-9/+1
| | | | | | | | | | | | This was the only state tracker emitting it, and hardware was just having to lower it anyway (or failing to lower it at all). v2: Extracted from a larger patch by Jose (which also dropped DP2A), fixed to actually not reference TGSI_OPCODE_CND. Change by anholt. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Axel Davy <[email protected]> Reviewed-by: David Heidelberg <[email protected]>
* nine: Don't reference the dead TGSI_OPCODE_NRM.Jose Fonseca2014-11-241-1/+1
| | | | | | | | | | The translation is lowering it to not using TGSI_OPCODE_NRM, anyway. v2: Extracted from a larger patch by Jose that also dropped DP2A usage. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Axel Davy <[email protected]> Reviewed-by: David Heidelberg <[email protected]>
* nine: Don't use the otherwise-dead SFL opcode in an unreachable path.Eric Anholt2014-11-241-1/+1
| | | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Axel Davy <[email protected]> Reviewed-by: David Heidelberg <[email protected]>
* util: Prefer atomic intrinsics to inline assembly.Matt Turner2014-11-241-2/+2
| | | | | | | | | | | | | Cuts a little more than 1k of .text size from i915g. This was previously done in commit 5f66b340 and subsequently reverted in commit 3661f757 after bug 30514 was filed. I believe the cause of bug 30514 wasn't anything related to cross compiling, but rather that the toolchain used defaulted to -march=i386, and i386 doesn't have the CMPXCHG or XADD instructions used to implement the intrinsics. So we reverted a patch that improved things so that we didn't break compilation for a platform that never could have worked anyway.
* vc4: Fix some inconsistent indentation.Eric Anholt2014-11-241-6/+6
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* vc4: Don't forget to actually connect the fence code.Eric Anholt2014-11-241-0/+2
| | | | I thought I'd tested this.
* vc4: Add a note about a piece of errata I've learned about.Eric Anholt2014-11-241-0/+4
| | | | | Right now in my environment I've only got a small CMA area, so this constraint ends up holding.
* r600g: do all CUBE ALU operations before gradient texture operations (v2.1)Dave Airlie2014-11-241-64/+72
| | | | | | | | | | | | | This moves all the CUBE section above the gradients section, so that the gradient emission happens on one block which is what sb/hardware expect. v2: avoid changes to bytecode by using spare temps v2.1: shame gcc, oh the shame. (uninit var warnings) Cc: "10.4 10.3" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix texture gradients instruction emission (v2)Dave Airlie2014-11-241-28/+31
| | | | | | | | | | | | | | | | | | | The piglit tests were failing, and it appeared to be SB optimising out things, but Glenn pointed out the gradients are meant to be clause local, so we should emit the texture instructions in the same clause. This moves things around to always copy to a temp and then emit the texture clauses for H/V. v2: Glenn pointed out we could get another ALU fetch in the wrong place, so load the src gpr earlier as well. Fixes at least: ./bin/tex-miplevel-selection textureGrad 2D Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.4 10.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50,nvc0: buffer resources can be bound as other things down the lineIlia Mirkin2014-11-232-14/+14
| | | | | | | | | res->bind is not an indicator of how the resource is currently bound. buffers can be rebound across different binding points without changing underlying storage. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* nv50,nvc0: actually check constbufs for invalidationIlia Mirkin2014-11-232-3/+6
| | | | | | | | The number of vertex buffers has nothing to do with the number of bound constbufs. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* nv50/ir: set neg modifiers on min/max argsIlia Mirkin2014-11-231-0/+2
| | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=86618 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]>
* i915g: Fallback copy_render for ZS formatsStéphane Marchesin2014-11-221-1/+11
| | | | | | | These don't work out of the box, need more work, maybe with a proxy format? Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Add back 4444 and 5551 formatsStéphane Marchesin2014-11-222-2/+4
| | | | | | Now that we have the transfers working, we can re-add those formats. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't limit blitter to POT texturesStéphane Marchesin2014-11-221-3/+2
| | | | | | | Now that we have NPOT support for u_blitter, there is no reason to limit this any longer. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Align all texture dimensions to the next POTStéphane Marchesin2014-11-221-28/+29
| | | | | | | | This creates a usable layout for all NPOT textures. Of course these still have lots of limitations, but at least we can render to a level. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix typosStéphane Marchesin2014-11-221-2/+2
| | | | Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix maxlod computation.Stéphane Marchesin2014-11-221-3/+3
| | | | Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Fix offset for level != 0Stéphane Marchesin2014-11-225-8/+27
| | | | | | | | For NPOT texture layouts, we want to be able to access texture levels other than 0 directly. Since the hw doesn't support that, We do it by adding the offset directly. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't write constants past I915_MAX_CONSTANTStéphane Marchesin2014-11-221-1/+1
| | | | | | | | This happens with glsl-convolution-1, where we have 64 constants. This doesn't make the test pass (we don't have 64 constants anyway, only 32) but this prevents it from crashing. Signed-off-by: Stéphane Marchesin <[email protected]>
* i915g: Don't hardcode array size for phase countStéphane Marchesin2014-11-221-1/+1
| | | | | | This is an array of temp registers, so use I915_MAX_TEMPORARY for the size. Signed-off-by: Stéphane Marchesin <[email protected]>
* draw: allow LLVM use on non-SSE2 X86 cpusDavid Heidelberg2014-11-221-14/+1
| | | | | | | | | | | | | | | | This patch remove workaround related to LLVM < 3.2 bug. Original bug has been closed as fixed in 2011. At this moment gallium requires LLVM 3.3 (2013). LLVM has been tested without SSE2 support in commit ca70de9bd20bc4a11b2d2d368e0cc1f49527a947 and removed after requiring LLVM 3.3 in commit 013ff2fae13da41c2f5619c4698b0a7b5aa6a06d Original LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=6960 Signed-off-by: David Heidelberg <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodesMarek Olšák2014-11-211-0/+7
| | | | | | | So far it has been compiled into pretty ugly code (8 instructions or so for either opcode). Reviewed-by: Tom Stellard <[email protected]>
* vc4: Update for new kernel ABI with async execution and waits.Eric Anholt2014-11-209-3/+250
| | | | | Our submits now return immediately and you have to manually wait for things to complete if you want to (like a normal driver).
* rtasm,translate: Re-enable SSE on Mingw64.José Fonseca2014-11-202-2/+2
| | | | | | | | | | | This reverts f4dd0991719ef3e2606920c5100b372181c60899. The src/gallium/tests/unit/translate_test.c gives the same results on MinGW 64-bits as on Linux 64-bits. And since MinGW is often used for development/testing due to its convenience, it's better not to have this sort of differences relative to MSVC. Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: remove unused variable si_state_dsa::db_render_controlMarek Olšák2014-11-191-1/+0
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* llvmpipe: enable PIPE_CAP_TGSI_VS_LAYER_VIEWPORTRoland Scheidegger2014-11-191-0/+1
| | | | | | | | | | | | No changes required in the driver itself, all handled by draw. piglit results in a quick run: skip->pass 7 skip->fail 2 (The new failures in the ARB_fragment_layer_viewport group are expected, we fail the same if gs doesn't write these outputs regardless of the vs.) Reviewed-by: Jose Fonseca <[email protected]>
* draw: fixes for vertex shaders outputting layer or viewport indexRoland Scheidegger2014-11-197-17/+21
| | | | | | | | | | Mostly add a couple cases so we don't just check gs for this. There's only one gotcha, the built-in vp transform in the llvm vs can't handle it (this would be fixable though non-trivial due to vp index being non-constant for the SoA outputs, but we don't use it if there's a gs neither - the whole clip/vp transform integration there is suboptimal). Reviewed-by: Jose Fonseca <[email protected]>
* st/va: surface: render subpictureMichael Varga2014-11-191-0/+120
| | | | Signed-off-by: Michael Varga <[email protected]>
* st/va: subpicture implementationMichael Varga2014-11-192-13/+161
| | | | | | | | | added BGRA format create/destroy set image associate/deassociate Signed-off-by: Michael Varga <[email protected]>
* st/va: added internal storage for VAImage and BGRA formatMichael Varga2014-11-192-26/+48
| | | | | | | When calling vaCreateImage() an internal copy of VAImage is maintained since the allocation of "image" may not be guaranteed to live long enough. Signed-off-by: Michael Varga <[email protected]>
* st/va: added some calls to handle_table_remove()Michael Varga2014-11-193-0/+3
| | | | | | In a few locations handles were being added but not removed. Signed-off-by: Michael Varga <[email protected]>
* r600g: limit texture offset application to specific types (v2)Dave Airlie2014-11-191-3/+18
| | | | | | | | | | | | | | | | | | | | | | For 1D and 2D arrays we don't want the other coordinates being offset and affecting where we sample. I wrote this patch 6 months ago but lost it. Fixes: ./bin/tex-miplevel-selection textureLodOffset 1DArray ./bin/tex-miplevel-selection textureLodOffset 2DArray ./bin/tex-miplevel-selection textureOffset 1DArray ./bin/tex-miplevel-selection textureOffset 1DArrayShadow ./bin/tex-miplevel-selection textureOffset 2DArray ./bin/tex-miplevel-selection textureOffset(bias) 1DArray ./bin/tex-miplevel-selection textureOffset(bias) 2DArray v2: rewrite to handle more cases and be consistent with code above. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.3 10.4" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: geom shaders: always load texture src regs from inputsDave Airlie2014-11-191-1/+2
| | | | | | | | | | | Otherwise we seem to lose the split_gs_inputs and try and pull from an uninitialised register. fixes 9 texelFetch geom shader tests. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.3 10.4" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Emit semaphore instructions for new kernel ABI.Eric Anholt2014-11-183-6/+87
| | | | | | | Previously, the kernel would dispatch thread 0, wait, then dispatch thread 1. By insisting that the thread contents use semaphores in the right place, the kernel can sleep for longer by dispatching both threads at once.
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