summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Expand)AuthorAgeFilesLines
* u_simple_shaders: try to un-break the Windows buildNicolai Hähnle2016-11-161-2/+3
* radeonsi: fix a subtle bounds checking corner case with 3-component attributesNicolai Hähnle2016-11-163-2/+39
* radeonsi: reject some 3-component formats as buffer texturesNicolai Hähnle2016-11-161-8/+35
* util/blitter: add clamping during SINT <-> UINT blitsNicolai Hähnle2016-11-166-43/+125
* util/blitter: index texfetch_col shaders by typeNicolai Hähnle2016-11-161-35/+19
* swr: mark color clamping as unsupportedIlia Mirkin2016-11-151-2/+3
* swr: always enable adding start/base vertex to gl_VertexIdIlia Mirkin2016-11-151-0/+1
* swr: add support for upper-left fragcoord positionIlia Mirkin2016-11-151-2/+8
* swr: make sure that all rendering is finished on shader destroyIlia Mirkin2016-11-151-0/+8
* swr: disable blending for integer formatsIlia Mirkin2016-11-151-0/+3
* swr: mark rgb9_e5 as unrenderableIlia Mirkin2016-11-151-1/+1
* swr: no support for shader stencil exportIlia Mirkin2016-11-151-1/+1
* swr: mark both frag and vert textures read, don't forget about cbsIlia Mirkin2016-11-151-5/+15
* swr: fix texture layout for compressed formatsIlia Mirkin2016-11-152-4/+6
* swr: add archrast generated files to gitignoreIlia Mirkin2016-11-151-0/+4
* swr: [rasterizer jitter] don't bother quantizing unused channelsIlia Mirkin2016-11-151-1/+1
* swr: [rasterizer memory] fix store tile for 128-bit ymajor tilingIlia Mirkin2016-11-151-1/+1
* swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formatsIlia Mirkin2016-11-152-0/+2
* radeonsi: set IF_THRESHOLD to 3Marek Olšák2016-11-151-1/+2
* gallium: add PIPE_SHADER_CAP_LOWER_IF_THRESHOLDMarek Olšák2016-11-1514-0/+21
* gallivm: limit use of setFastMathFlags to LLVM 3.8 and laterMarek Olšák2016-11-151-0/+2
* radeonsi: set unsafe fpmath on FP instructions when allowed by R600_DEBUGMarek Olšák2016-11-151-1/+5
* gallivm: add lp_create_builder with an unsafe_fpmath optionMarek Olšák2016-11-152-0/+17
* radeonsi: fold some shader context initialization to si_llvm_context_initMarek Olšák2016-11-153-29/+30
* clover: adapt to new error API since LLVM r286752Vedran Miletić2016-11-141-2/+8
* swr: [rasterizer core] remove driverTypeTim Rowley2016-11-145-49/+2
* swr: [rasterizer archrast] move to pass by valueTim Rowley2016-11-142-2/+2
* swr: [rasterizer core] add mode for aux buffer in the SWR_SURFACE_STATETim Rowley2016-11-141-0/+16
* swr: [rasterizer common] don't bleed NOMINMAX definition after <windows.h>Tim Rowley2016-11-141-1/+4
* swr: [rasterizer archrast] add eventsTim Rowley2016-11-146-6/+541
* swr: [rasterizer core] fix culling issuesTim Rowley2016-11-141-66/+119
* swr: [rasterizer core/jitter] fix alpha test bugTim Rowley2016-11-143-3/+15
* swr: [rasterizer core] various code style changesTim Rowley2016-11-146-5/+26
* swr: [rasterizer archrast] don't generate empty filesTim Rowley2016-11-144-8/+39
* swr: [rasterizer archrast] fix open file handle limit issueTim Rowley2016-11-141-6/+44
* swr: [rasterizer archrast] fix double free issueTim Rowley2016-11-149-24/+41
* swr: [rasterizer core] separate frontend/backend stats enablesTim Rowley2016-11-146-26/+51
* swr: [rasterizer core] 16-wide tile store nearly completedTim Rowley2016-11-145-314/+917
* vc4: Add simulator kernel validation for multithreaded fragment shaders.Jonas Pfeil2016-11-123-5/+76
* vc4: Mark threaded FSes as non-singlethread in the CL.Eric Anholt2016-11-123-1/+6
* vc4: Flag the last thread switch in the program as the last.Eric Anholt2016-11-123-0/+34
* vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.Eric Anholt2016-11-122-0/+49
* vc4: Add some spec citations about texture fifo management.Eric Anholt2016-11-121-5/+37
* vc4: Use ra14/rb14 as the spilling registers.Eric Anholt2016-11-122-8/+8
* vc4: Add support for register allocation for threaded shaders.Eric Anholt2016-11-123-20/+85
* vc4: Split register class setup for physical files from accumulators.Eric Anholt2016-11-121-17/+19
* vc4: Use register allocator CLASS_BIT_R0_R3 to clean up CLASS_B.Eric Anholt2016-11-121-4/+4
* vc4: Add support for QPU scheduling of thread switch instructions.Eric Anholt2016-11-121-2/+27
* vc4: Add a thread switch QIR instruction.Eric Anholt2016-11-123-0/+18
* vc4: Add a bit of QPU validation for threaded shaders.Eric Anholt2016-11-121-1/+102
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 07:59:17 +0000