| Commit message (Collapse) | Author | Age | Files | Lines |
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Previously the first provoking vertex convention would only be used if
flatshading were enabled. No matter how I look at it that cannot be possibly
correct. Maybe the code getting used was somewhat simpler that way at a time
where there weren't constant interpolated attributes, only flatshading...
(Note that all other places including the decomposition macros already do
the same.)
Reviewed-by: Jose Fonseca <[email protected]>
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This stage only worked for traditional old-school flatshading, it did ignore
constant interpolated values and only handled colors, the code probably
predates using of constant interpolated values in gallium. So fix this - the
clip stage apparently did this a long time ago already.
Unfortunately this also means the stage needs to be invoked when flatshading
isn't enabled but some other prim changing stages are - for instance with
fill mode line each of the 3 lines in a tri should get the same attribute
value from the leading vertex in the original tri if interpolation is constant,
which did not happen before
Due to that, the stage is now run in more cases, even unnecessary ones. Could
in theory skip it completely if there aren't any constant interpolated
attributes (and rast->flatshade isn't set), but not sure it's worth bothering,
as it looks kinda complicated getting this information in advance.
No piglit change (doesn't really cover this directly).
Reviewed-by: Jose Fonseca <[email protected]>
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Just like we do for tris (det shouldn't matter at this point, however
can have flags for things like line stipple reset).
No piglit change, it would fail line stippling tests if the flatshade
stage were run, which will happen with the next commit.
Reviewed-by: Jose Fonseca <[email protected]>
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The previous language was a bit misleading, since it sounded like
w was interpolated then the reciprocal calculated which isn't what
should be happening.
Reviewed-by: Jose Fonseca <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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I'm not sure if GS hw outputs line lists or line strips.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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It's used only if VGT_SHADER_STAGES_EN.DISPATCH_DRAW_EN is 1, which we don't
set.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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v2: added a helper function for invalidation of the sh constants
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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This huge amount of code deserves its own file.
Reviewed-by: Michel Dänzer <[email protected]>
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The big function is split into 3 smaller functions.
Reviewed-by: Michel Dänzer <[email protected]>
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An assertion should suffice.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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* Use print macro to fix warning on 64-bit systems
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* Can be redefined on some platforms through u_debug.h
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This way we get a warning if an enum value is not handled.
v2: codestyle
Signed-off-by: Jan Vesely <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
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On evergreen there are 4 regs, on r600/700 there is only one.
Don't initialise regs and trash someone elses state.
Not sure this fixes anything, but hey one less stupid.
Reviewed-By: Glenn Kennard <[email protected]>
Cc: "10.3 10.4" [email protected]
Signed-off-by: Dave Airlie <[email protected]>
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This means another pass of reordering the uniform data store, but it lets
us pair up a lot more instructions.
total instructions in shared programs: 44639 -> 43176 (-3.28%)
instructions in affected programs: 36938 -> 35475 (-3.96%)
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This is a standard scheduling heuristic, and clearly helps.
total instructions in shared programs: 46418 -> 44467 (-4.20%)
instructions in affected programs: 42531 -> 40580 (-4.59%)
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These don't have raddr fields.
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Fixes assertion failures if we adjust scheduling priorities to emphasize
VPM reads more.
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An immediate load overwrites the mul and add operations, so you can't
merge with them.
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Signed-off-by: Aaron Watry <awatry at gmail.com>
Reviewed-by: Tom Stellard <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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On a3xx, lower TXP for 3D textures, on a4xx lower all TXP.
Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Collapse things back into a setup_slices() which takes the desired
alignment as a param. This gets things ready for a4xx which has some
slightly different requirements.
Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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v2: actually do perspective divide for RECT/SHADOWRECT
Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Required by Nine. Tested with util_run_tests.
It's added to softpipe, llvmpipe, and r300g/swtcl.
Tested-by: David Heidelberg <[email protected]>
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This increases the cost of a raddr b conflict spill (save r3 to rb31, move
src1 to r3, move rb31 back to r3 when done, instead of just move src1 to
r3), but on average thanks to instruction pairing it's more worthwhile to
have another accumulator.
total instructions in shared programs: 46428 -> 46171 (-0.55%)
instructions in affected programs: 38030 -> 37773 (-0.68%)
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The register allocator walks from the end of the nodes array looking for
trivially-allocatable things to put on the stack, meaning (assuming
everything is trivially colorable and gets put on the stack in a single
pass) the low node numbers get allocated first. The things allocated
first happen to get the lower-numbered registers, which is to say the fast
accumulators that can be paired more easily.
When we previously made the nodes match the temporary register numbers,
we'd end up putting the shader inputs (VS or FS) in the accumulators,
which are often long-lived values. By prioritizing the shortest-lived
values for allocation, we can get a lot more instructions that involve
accumulators, and thus fewer conflicts for raddr and WS.
total instructions in shared programs: 52870 -> 46428 (-12.18%)
instructions in affected programs: 52260 -> 45818 (-12.33%)
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Since d8da6deceadf5e48201d848b7061dad17a5b7cac where the
state tracker started using UCMP on cayman a number of tests
regressed.
this seems to be r600g is doing CNDGE_INT for UCMP which is >= 0,
we should be doing CNDE_INT with reverse arguments.
Reviewed-by: Glenn Kennard <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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See commit 2b7a972e for the Coccinelle script.
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
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