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* swr: [rasterizer core] Finish SIMD16 PA OPT including tesselationTim Rowley2017-03-201-21/+247
* swr: [rasterizer core] Finish SIMD16 PA OPT except tesselationTim Rowley2017-03-202-274/+1405
* swr: [rasterizer core] Support sparse numa id values on all OSesTim Rowley2017-03-201-27/+53
* r600g/sb: Fix memory leak by reworking uses list (rebased)Constantine Kharlamov2017-03-204-61/+28
* radeonsi: check the IR type before waiting for a compute compilation fenceMarek Olšák2017-03-201-1/+3
* si_descriptor: move velems nullity check before dereferenceJulien Isorce2017-03-201-4/+11
* radeon_drm_bo: explicitly check return value of drmCommandWriteReadJulien Isorce2017-03-201-2/+7
* si_pipe: remove nullity check after dereferenceJulien Isorce2017-03-201-3/+0
* radeon: initialize hole variable before calling container_ofJulien Isorce2017-03-201-1/+1
* r600g: Fix out of bounds accessBartosz Tomczyk2017-03-202-20/+22
* r600g: update sb documentationConstantine Kharlamov2017-03-201-3/+6
* r600g: make condition clearerConstantine Kharlamov2017-03-201-6/+8
* nv30: create uploader after pipe->screen is setIlia Mirkin2017-03-191-6/+6
* nv50,nvc0: enable TEX_LZ and TXF_LZIlia Mirkin2017-03-183-4/+17
* nvc0/ir: treat FMA like MAD for operand propagationKarol Herbst2017-03-181-0/+1
* st/dri: wait for thread to finish before unbinding contextTimothy Arceri2017-03-181-0/+3
* gallium/radeon: formalize that create_batch_query doesn't need pipe_contextMarek Olšák2017-03-173-13/+12
* gallium/radeon: formalize that create_query doesn't need pipe_contextMarek Olšák2017-03-173-32/+32
* gallium/radeon: reference pipe_resource in pipe_transferMarek Olšák2017-03-172-2/+5
* radeonsi: compile all TGSI compute shaders asynchronouslyMarek Olšák2017-03-171-44/+81
* radeonsi: require that compiler threads are enabledMarek Olšák2017-03-172-11/+13
* trace: remove leftover assertions after pipe_resource wrapping removalMarek Olšák2017-03-171-6/+0
* gallium/u_upload: make the first persistent mapping unsynchronizedMarek Olšák2017-03-171-0/+1
* gallium: implement the backend of threaded GL dispatchMarek Olšák2017-03-164-0/+56
* gallivm: (trivial) remove duplicated lineRoland Scheidegger2017-03-161-1/+0
* draw: (trivial) remove a unnecessary lp_build_alloca()Roland Scheidegger2017-03-161-2/+0
* swr: support layer output in geometry shadersIlia Mirkin2017-03-151-0/+2
* gallium/tgsi: Treat UCMP sources as floats to match the GLSL-to-TGSI pass exp...Francisco Jerez2017-03-152-16/+46
* swr: validate backend state numAttributesTim Rowley2017-03-151-0/+2
* radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-152-6/+16
* gallium: add TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-154-5/+39
* gallium: add PIPE_CAP_TGSI_TEX_TXF_LZMarek Olšák2017-03-1517-0/+18
* radeonsi: disable sinking common instructions down to the end blockSamuel Pitoiset2017-03-151-0/+11
* tgsi: add missing compute shader entry in tgsi_get_processor_name()Samuel Pitoiset2017-03-151-0/+2
* radeonsi: clean up tex_fetch_ptrs()Samuel Pitoiset2017-03-151-6/+4
* winsys/amdgpu: use drmGetDevice2 APIEmil Velikov2017-03-151-2/+2
* r600: refactor binding code for attach buffer to CB.Dave Airlie2017-03-151-33/+78
* r600: refactor out CB setup.Dave Airlie2017-03-151-104/+143
* r600: refactor texture resource words setup code.Dave Airlie2017-03-151-88/+131
* r600: factor out the code to initialise a buffer resource.Dave Airlie2017-03-151-29/+51
* r600g: make framebuffer atom rely on dual src blend state.Dave Airlie2017-03-154-2/+7
* nir: Rework conversion opcodesJason Ekstrand2017-03-145-22/+22
* gallium/radeon: disable the shader cache if dumping shadersMarek Olšák2017-03-131-0/+5
* radeonsi: mark all bound shader buffer ranges as initializedMarek Olšák2017-03-131-0/+3
* gallium/hud: check NULL return from u_upload_allocJulien Isorce2017-03-131-0/+5
* winsys/radeon: check null return from radeon_cs_create_fence in cs_flushJulien Isorce2017-03-131-11/+13
* winsys/radeon: check null in radeon_cs_create_fenceJulien Isorce2017-03-131-0/+3
* freedreno/ir3: fragz cannot be half precisionRob Clark2017-03-131-0/+6
* freedreno/ir3: optimize less in glslRob Clark2017-03-131-1/+1
* svga: handle P016 format as wellChristian König2017-03-131-0/+1
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