index
:
mesa.git
gallium_va_encpackedheader01
master
Unnamed repository; edit this file 'description' to name the repository.
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
gallium
Commit message (
Expand
)
Author
Age
Files
Lines
*
meson: Revert commit overriding C++ standard with gnu++11 on ppc64el
Frédéric Bonnard
2020-06-30
1
-4
/
+0
*
clover: Fix types collision between c++ and altivec
Frédéric Bonnard
2020-06-30
1
-0
/
+5
*
panfrost: Do fine-grained flushing for occlusion query results
Icecream95
2020-06-30
2
-3
/
+9
*
freedreno/a4xx: fix *_NONE enum conversion
Shawn Guo
2020-06-30
2
-8
/
+8
*
radeonsi: add a debug option to enable NGG culling for tessellation
Marek Olšák
2020-06-30
4
-8
/
+15
*
radeonsi: don't try to enable NGG culling for GS
Marek Olšák
2020-06-30
1
-1
/
+2
*
radeonsi: always use Wave64 for HS/GS/VS shader stages (except GS fast launch)
Marek Olšák
2020-06-30
1
-4
/
+8
*
radeonsi: always use Wave32 for GS fast launch, because Wave64 hangs
Marek Olšák
2020-06-30
4
-6
/
+19
*
radeonsi: fix NGG culling for Wave64
Marek Olšák
2020-06-30
4
-14
/
+23
*
radeonsi: don't flush in fence_server_sync
Marek Olšák
2020-06-30
1
-5
/
+8
*
radeonsi: bump SI_NUM_SHADER_BUFFERS to 32
Pierre-Eric Pelloux-Prayer
2020-06-30
5
-35
/
+40
*
zink: set lower_uadd_carry in nir options
Mike Blumenkrantz
2020-06-29
1
-0
/
+1
*
v3d: Fix -Wmaybe-uninitialized compiler warning in the v33 code.
Eric Anholt
2020-06-29
1
-2
/
+4
*
v3d: Enable PIPE_CAP_TGSI_TEXCOORD.
Eric Anholt
2020-06-29
1
-0
/
+1
*
vc4: Enable PIPE_CAP_TGSI_TEXCOORD.
Eric Anholt
2020-06-29
3
-18
/
+7
*
gallium/util: Add a helper function for point sprite handling.
Eric Anholt
2020-06-29
1
-0
/
+19
*
frontends/va: Handle dynamic resolution/SVC for VP9
Satyajit Sahu
2020-06-29
2
-6
/
+16
*
gallivm/nir: fix const loading on big endian systems
Dave Airlie
2020-06-29
1
-1
/
+1
*
rbug: Fix rbug_delete_vs_state lock acquisition.
Vinson Lee
2020-06-27
1
-1
/
+1
*
v3d: moving v3d simulator to src/broadcom
Alejandro Piñeiro
2020-06-27
8
-1181
/
+5
*
iris: Implement pipe->texture_subdata directly
Kenneth Graunke
2020-06-26
1
-1
/
+79
*
freedreno/ir3: disk-cache support
Rob Clark
2020-06-26
1
-0
/
+14
*
freedreno/ir3: build binning variant at same time as draw variant
Rob Clark
2020-06-26
1
-4
/
+8
*
freedreno/a6xx+ir3: stop generating pointless binning shaders
Rob Clark
2020-06-26
2
-12
/
+8
*
freedreno/ir3: add ir3_compiler_destroy()
Rob Clark
2020-06-26
1
-1
/
+4
*
freedreno/ir3: move finalize_nir to pscreen hook
Rob Clark
2020-06-26
6
-0
/
+19
*
freedreno/ir3: add ir3_finalize_nir()
Rob Clark
2020-06-26
1
-1
/
+1
*
zink: use OpFUnordNotEqual for nir_op_fne
Mike Blumenkrantz
2020-06-26
1
-1
/
+1
*
zink: set lower_mul_high and lower_rotate in ntv compiler options
Mike Blumenkrantz
2020-06-26
1
-0
/
+2
*
zink: handle isign alu in ntv
Mike Blumenkrantz
2020-06-26
1
-0
/
+1
*
zink: handle ixor in ntv
Mike Blumenkrantz
2020-06-26
1
-0
/
+1
*
zink: lower byte/word extract ops in nir
Mike Blumenkrantz
2020-06-26
1
-0
/
+2
*
zink: add bitfield_reverse handling to ntv
Mike Blumenkrantz
2020-06-26
1
-0
/
+1
*
zink: add ult handling for ntv
Mike Blumenkrantz
2020-06-26
1
-0
/
+1
*
zink: handle signed and unsigned min/max ops in ntv
Mike Blumenkrantz
2020-06-26
1
-0
/
+4
*
panfrost: Add PAN_MESA_DEBUG=gl3 flag
Icecream95
2020-06-26
1
-5
/
+21
*
freedreno/a6xx: use firstIndex field
Connor Abbott
2020-06-26
1
-3
/
+2
*
freedreno: On a5xx+ INDX_SIZE is MAX_INDICES
Connor Abbott
2020-06-26
3
-14
/
+14
*
freedreno: Share constlen between different stages properly
Connor Abbott
2020-06-26
2
-8
/
+42
*
freedreno: Refactor ir3_cache shader compilation
Connor Abbott
2020-06-26
1
-22
/
+29
*
ir3, freedreno: Round up constlen earlier
Connor Abbott
2020-06-26
5
-10
/
+12
*
radeonsi: remove tabs
Marek Olšák
2020-06-26
9
-56
/
+56
*
radeonsi: clear per-context buffers at the end of si_create_context
Marek Olšák
2020-06-26
1
-5
/
+11
*
radeonsi: make si_pm4_cmd_begin/end static and simplify all usages
Marek Olšák
2020-06-26
4
-15
/
+8
*
radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state
Marek Olšák
2020-06-26
4
-36
/
+4
*
radeonsi: make wait_mem_scratch unmappable
Marek Olšák
2020-06-26
1
-1
/
+4
*
radeonsi: don't add the tess ring buffers into the cs_preamble state
Marek Olšák
2020-06-26
2
-3
/
+5
*
radeonsi: rename init_config states to cs_preamble states
Marek Olšák
2020-06-26
7
-47
/
+45
*
radeonsi: don't add the border color buffer into the init_config state
Marek Olšák
2020-06-26
2
-1
/
+3
*
ac,winsys/amdgpu: align IBs the same as the kernel
Marek Olšák
2020-06-26
1
-11
/
+16
[next]