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* gallium: Add PIPE_SHADER_CAP_FP16Jan Vesely2017-09-1816-0/+27
| | | | | | | | | Denotes native half precision float operations capability v2: PIPE_CAP_HALFS -> PIPE_SHADER_CAP_FP16 fix indentation Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: fix compile errorBenedikt Schemmer2017-09-181-1/+1
| | | | | | | Fixes: 3f6b3d9db ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE") Signed-off-by: Benedikt Schemmer <[email protected]> Previously-pointed-out-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allow out-of-order rasterization in commutative blending casesNicolai Hähnle2017-09-185-4/+68
| | | | | | | | | | | | We do not enable this by default for additive blending, since it slightly breaks OpenGL invariance guarantees due to non-determinism. Still, there may be some applications can benefit from white-listing via the radeonsi_commutative_blend_add drirc setting without any real visible artifacts. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: add drirc option "radeonsi_assume_no_z_fights"Nicolai Hähnle2017-09-184-4/+8
| | | | | | | | | | | | | | This option enables a performance optimization where typical non-blending draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE chips). This optimization can lead to incorrect results when an applications renders multiple objects with the same Z value at the same pixel, so we will never enable it by default. But there may be applications that could benefit from white-listing. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: enable out-of-order rasterization when possible on VI and GFX9 dGPUsNicolai Hähnle2017-09-187-6/+193
| | | | | | | | | This does not take commutative blending into account yet. R600_DEBUG=nooutoforder disables it. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: pass old_(perfect_)enable to set_occlusion_query_stateNicolai Hähnle2017-09-184-4/+11
| | | | | | | The callee can derive the current enable state itself. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVENicolai Hähnle2017-09-1823-11/+93
| | | | | | | | | | | | | | | | | To be able to properly distinguish between GL_ANY_SAMPLES_PASSED and GL_ANY_SAMPLES_PASSED_CONSERVATIVE. This patch goes through all drivers, having them treat the two query types identically, except: 1. radeon incorrectly enabled conservative mode on PIPE_QUERY_OCCLUSION_PREDICATE. We now do it correctly, only on PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE. 2. st/mesa uses the new query type. Fixes dEQP-GLES31.functional.fbo.no_attachments.* Reviewed-by: Marek Olšák <[email protected]>
* amd/common: remove has_ds_bpermute argument from ac_build_ddxyNicolai Hähnle2017-09-183-4/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: add chip_class to ac_llvm_contextNicolai Hähnle2017-09-181-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: round cube array slice in ac_prepare_cube_coordsNicolai Hähnle2017-09-181-0/+1
| | | | | | | | | | | | The NIR-to-LLVM pass already does this; now the same fix covers radeonsi as well. Fixes various tests of dEQP-GLES31.functional.texture.filtering.cube_array.combinations.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: workaround for gather4 on integer cube mapsNicolai Hähnle2017-09-181-6/+100
| | | | | | | | | | This is the same workaround that radv already applied in commit 3ece76f03dc0 ("radv/ac: gather4 cube workaround integer"). Fixes dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i/ui.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* clover: Fix build after LLVM r313390Jan Vesely2017-09-152-1/+11
| | | | | | | v2: pass llvm context reference instead of a pointer Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/omx_bellagio: Rename state tracker and optionGurkirpal Singh2017-09-1515-7/+7
| | | | | | | | Changes --enable-omx option to --enable-omx-bellagio Signed-off-by: Gurkirpal Singh <[email protected]> Reviewed-and-Tested-by: Julien Isorce <[email protected]> Acked-by: Christian König <[email protected]>
* r600: add .gitignore for egd_tables.hDave Airlie2017-09-151-0/+1
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* radeonsi: enable STD430 packing of UBOs by defaultTimothy Arceri2017-09-151-1/+1
| | | | | | | Before this change we were defaulting to STD140 which is slightly less efficient at packing arrays. Reviewed-by: Marek Olšák <[email protected]>
* gallium: introduce PIPE_CAP_LOAD_CONSTBUFTimothy Arceri2017-09-1517-0/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make use of LOAD for UBOsTimothy Arceri2017-09-151-10/+21
| | | | | | v2: always set can_speculate and allow_smem to true Reviewed-by: Marek Olšák <[email protected]>
* gallium: add CONSTBUF type to tgsi_file_typeTimothy Arceri2017-09-152-0/+2
| | | | | | | This will be use to distinguish between load types when using the TGSI_OPCODE_LOAD opcode. Reviewed-by: Marek Olšák <[email protected]>
* virgl: drop const dimensions on first block.Dave Airlie2017-09-151-0/+27
| | | | | | | | | | | | The virgl protocol version of tgsi doesn't handle this yet, transform it back to the old ways. Thanks to Nicolai Hähnle <[email protected]> for also writing nearly the same patch. Fixes: 41e342d5 tgsi/ureg: always emit constants (and their decls) as 2D Tested-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move si_get_wave_info() to AMD common codeSamuel Pitoiset2017-09-141-93/+3
| | | | | | | | This will allow us to use it from radv. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* swr: use ARRAY_SIZE macroEric Engestrom2017-09-141-4/+6
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
* gallium/{r600, radeonsi}: Fix segfault with color format (v2)Denis Pauk2017-09-143-1/+17
| | | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102552 v2: Patch cleanup proposed by Nicolai Hähnle. * deleted changes in si_translate_texformat. Cc: Nicolai Hähnle <[email protected]> Cc: Ilia Mirkin <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: hard-code pixel center for interpolateAtSample without multisample ↵Nicolai Hähnle2017-09-133-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | buffers The GLSL rules for interpolateAtSample are unfortunate: "Returns the value of the input interpolant variable at the location of sample number sample. If multisample buffers are not available, the input variable will be evaluated at the center of the pixel. If sample sample does not exist, the position used to interpolate the input variable is undefined." This fix will fallback to monolithic shader compilation when interpolateAtSample is used without multisampling. One alternative would be to always upload 16 sample positions, filling the buffer up with repetition when the actual number of samples is less, and then ANDing the sample ID with 0xf. However, that punishes all well-behaving users of interpolateAtSample, when in reality, only conformance tests should be affected by the issue. Fixes dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.non_multisample_buffer.* Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: apply a mask to gl_SampleMaskIn in the PS prologNicolai Hähnle2017-09-133-5/+76
| | | | | | | | | | | | | gl_SampleMaskIn is supposed to contain set bits only for the samples that are covered by the current fragment shader invocation, but the VGPR initialization hardware loads the set of all bits that are covered at the current pixel. Fixes various tests in dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove SET_PREDICATION workaround on newer firmwareNicolai Hähnle2017-09-131-2/+4
| | | | | | We need to keep the workaround for older firmware, though. Reviewed-by: Marek Olšák <[email protected]>
* amd/common: get ME/PFP/CE firmware feature versions as wellNicolai Hähnle2017-09-131-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename variable to clarify its meaningNicolai Hähnle2017-09-131-10/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make si_init_shader_selector_async staticNicolai Hähnle2017-09-132-2/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix segfault in descriptor dumpingNicolai Hähnle2017-09-131-0/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: write out final driver log messages with GALLIUM_DDEBUG=alwaysNicolai Hähnle2017-09-133-2/+15
| | | | | | | | If the last operation happens to be a non-draw, such as a transfer_map that triggers a decompress blit, there may be interesting messages left in the driver log. Reviewed-by: Marek Olšák <[email protected]>
* swr/rast: Fetch compile state changesTim Rowley2017-09-133-6/+15
| | | | | | | | | | Add InstanceStrideEnable field and rename InstanceDataStepRate to InstanceAdvancementState in INPUT_ELEMENT_DESC structure. Add stubs for handling InstanceStrideEnable in FetchJit::JitLoadVertices() and FetchJit::JitGatherVertices() and assert if they are triggered. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: adjust linux cpu topology identification codeTim Rowley2017-09-131-43/+38
| | | | | | | Make more robust to handle strange strange configurations like a vmware exported 4-way numa X 1-core configuration. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Missed conversion to SIMD_TTim Rowley2017-09-131-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: whitespace changesTim Rowley2017-09-131-0/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add graph write to jit debug putputTim Rowley2017-09-131-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Migrate memory pointers to gfxptr_t typeTim Rowley2017-09-139-36/+36
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove hardcoded clip/cull slot from clipperTim Rowley2017-09-131-14/+21
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Start to remove hardcoded clipcull_dist vertex attrib slotTim Rowley2017-09-133-8/+15
| | | | | | | | Add new field in SWR_BACKEND_STATE::vertexClipCullOffset to specify the start of the clip/cull section of the vertex header. Removed use of hardcoded slot from binner. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move clip/cull enables in APITim Rowley2017-09-139-40/+40
| | | | | | Moved from from SWR_RASTSTATE to SWR_BACKEND_STATE. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add new API SwrStallBETim Rowley2017-09-132-0/+17
| | | | | | | | SwrStallBE stalls the backend threads until all work submitted before the stall has finished. The frontend threads can continue to make forward progress. Reviewed-by: Bruce Cherniak <[email protected]>
* Revert "winsys/amdgpu: disable local BOs on Raven"Marek Olšák2017-09-121-2/+1
| | | | | | This reverts commit 1cda9a2fee05effd9c64bd773bc6005281593662. It works now.
* radeonsi: optimize TCS epilog when invocation 0 writes tess factorsMarek Olšák2017-09-115-30/+89
| | | | | | | | | | This removes the barrier and LDS stores and loads for tess factors when it's possible. The removal of the barrier seems more important to me though. In one shader, it removes 17 * 4 bytes from the shader binary. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: add a new pass that analyzes tess factor writes (v2)Marek Olšák2017-09-112-0/+235
| | | | | | | | | | | | | | | | | | | The pass tries to deduce whether tess factors are always written by all shader invocations. The implication for radeonsi is that it doesn't have to use a barrier near the end of TCS, and doesn't have to use LDS for passing the tess factors to the epilog. v2: Handle barriers and do the analysis pass for each code segment surrounded by barriers separately, and AND results from all such segments writing tess factors. The change is trivial in the main switch statement. Also, the result is renamed to "tessfactors_are_def_in_all_invocs" to make the name accurate. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: use the new raw CS APIMarek Olšák2017-09-112-77/+93
| | | | | | This also cleans things up. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement pipe_context::fence_server_syncMarek Olšák2017-09-113-0/+68
| | | | | | This will be more useful once we have sync_file support. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: factor out some fence dependency code into separate functionsMarek Olšák2017-09-111-21/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: rename fence_dependency functionsMarek Olšák2017-09-111-12/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a proper fail path for calloc in r600_flush_from_stMarek Olšák2017-09-111-3/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: don't allow interprocess resource sharing for IBsMarek Olšák2017-09-111-1/+2
| | | | | | | Now we should get IB submissions with bo_list == NULL when DRI buffers aren't referenced. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix interprocess resource sharing on RavenMarek Olšák2017-09-111-1/+3
| | | | | | This kinda fragiile, but it at least unbreaks the driver. Reviewed-by: Nicolai Hähnle <[email protected]>
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