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* ilo: Initialize need_flush in draw_vbo.Vinson Lee2013-05-231-1/+1
| | | | | | | | | need_flush was uninitialized if hw3d->new_batch was true. Fixes "Uninitialized scalar variable" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* radeon: Initialize variables in radeon_llvm_context_init.Vinson Lee2013-05-221-0/+2
| | | | | | | | | | | 'type' was not fully initialized when calling lp_build_context_init. Fixes "Uninitialized scalar variable" defect reported by Coverity. NOTE: This is a candidate for the stable branches. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* softpipe: change TEX_TILE_SIZE and NUM_TEX_TILE_ENTRIESRoland Scheidegger2013-05-221-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Initially we had NUM_TEX_TILE_ENTRIES of 50, however this was using too much memory (mostly because the tile cache is operating on fixed max current sampler views which could be fixed but that's another topic). So it was decreased to 4. However this is a ridiculously low number which can't actually really work (the number of tiles needed for as little as a single quad with linear_mipmap_linear is 2 to 8 for a 2d texture, and 4 to 16 for a 3d texture), as it just about guarantees there will be cache thrashing sometimes (just about always for 3d textures in fact, since while there are 4 entries the cache is direct mapped). So increase that number to 16 (which is still on the low side for direct mapped cache though I guess using something like 4-way associativity would be more effective than increasing this further) which has at least some good chance to avoid thrashing. Since we don't want to increase memory requirements however in turn decrease the tile size accordingly from 64 to 32 (as a bonus point this also decreases the cost of texture thrashing which might still happen sometimes). I've seen performance improvement in the order of factor ~200 (specifically, drawing the first frame from the replay from bug 41787 needs "only" ~10s instead of ~30min, meaning I can actually compare the output with other drivers...) with this. Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: disambiguate TILE_SIZE / TEX_TILE_SIZERoland Scheidegger2013-05-223-38/+38
| | | | | | | These can be different (just like NUM_TEX_TILE_ENTRIES / NUM_ENTRIES), though currently they aren't. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: disable simple_shader optimizationRoland Scheidegger2013-05-221-1/+6
| | | | | | | | | | | | | | This optimization disabled mask checks if the shader is simple enough. While this should work correctly, the problem is that it can hide real issues because shaders in practice are usually complex enough (8 instructions or 1 texture is already enough) so this doesn't get used, whereas dumbed-down tests which should hit all the same code paths suddenly do something quite different. This was the reason that bug 41787 could not be easily tracked as stencil test not working correctly (piglit would in fact have failed some tests without that optimization). So disable it for now, it's unclear if it's much of a win in any case. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix early depth test / late depth write stencil issuesRoland Scheidegger2013-05-221-5/+12
| | | | | | | | | | | | | | We actually did early depth/stencil test and late depth/stencil write even when the shader could kill the fragment (alpha test or discard). Since it matters for the new stencil value if the fragment is killed by depth/stencil test or by the shader (in which case it will not reach the depth/stencil test) this simply cannot work (we also would possibly skip writing the new stencil value due to mask checks but this is a secondary issue). So use late depth test / late depth write instead in this case. (No piglit changes as it doesn't seem to hit such bogus early depth test / late depth write path.) Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix issue with not writing new stencil valuesRoland Scheidegger2013-05-222-4/+7
| | | | | | | | | | | | | | | We did mask checks between depth/stencil testing and depth/stencil write. This meant that if the depth/stencil test killed off all fragments we never actually wrote the new stencil value. This issue affected all early/late test/write combinations. So move the mask check after depth/stencil write (for early depth test, could do the same for late depth test but might not be worth it at that point so just skip it there). This addresses https://bugs.freedesktop.org/show_bug.cgi?id=41787. Piglit does not hit this issue because of the simple_shader optimization in generate_fs_loop() which means we're skipping the mask checks. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: (trivial) remove confusing code in stencil testRoland Scheidegger2013-05-221-16/+11
| | | | | | | | | This was meant to disable some code which isn't needed when depth/stencil isn't written. However, there's more code which wouldn't be needed in that case so having the condition there was just odd (llvm will drop all the code anyway). Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix bug in early depth test / late depth write handlingRoland Scheidegger2013-05-221-6/+7
| | | | | | | Using wrong type if the format was less than 32bits. No piglit changes as it doesn't hit that path. Reviewed-by: Jose Fonseca <[email protected]>
* Haiku: Add Gallium winsys and target codeAlexander von Gluck IV2013-05-229-0/+589
| | | | | | | | | | | | * We generate a static library for Haiku Gallium targets as our port system combines the compiled rendering code into a modular ar for each module (for example, our port system combines llvm libsoftpipe.a libllvmpipe.a into a single ar for the Haiku build system. I'd like the Gallium hgl target scons build system to do this some day, however how is beyond me at the moment. This is a first step.
* ilo: set more fields of 3DSTATE_DEPTH_BUFFERChia-I Wu2013-05-221-48/+120
| | | | | | | | Set lod/layer related fields of 3DSTATE_DEPTH_BUFFER. Since we always point to a single level/layer, those fields are always zero and this commit effectively makes no change. While at it, make it easier to disable manual slice offset calculation.
* ilo: correctly set view extent in SURFACE_STATEChia-I Wu2013-05-222-85/+115
| | | | | | | The view extent was set to be the same as the depth while it should be set to the number of layers. It makes a difference for 3D textures. Also use this as a chance to clean up the code.
* ilo: avoid unnecessary emission of SO statesChia-I Wu2013-05-222-9/+15
| | | | | | No need to emit 3DSTATE_SO_BUFFER and 3DSTATE_SO_DECL_LIST when SO is disabled. As the implicit flush done by the commands is also gone, emit an explicit flush.
* radeonsi: Fix user clip planesMichel Dänzer2013-05-211-4/+3
| | | | | | 4 more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Handle TGSI_SEMANTIC_CLIPVERTEXMichel Dänzer2013-05-216-8/+86
| | | | | | 17 more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Initial support for multiple constant buffersMichel Dänzer2013-05-214-73/+119
| | | | | | | Just enough to support an additional internal constant buffer for the user clip planes. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Fix handling of TGSI_SEMANTIC_PSIZEMichel Dänzer2013-05-215-9/+17
| | | | | | Two more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: increase array size for shader inputs and outputsMarek Olšák2013-05-212-2/+4
| | | | | | | | | | | and add assertions to prevent buffer overflow. This fixes corruption of the si_shader struct. NOTE: This is a candidate for the 9.1 branch. [ Cherry-pick of r600g commit da33f9b919039442e9ab51f9b1d1c83a73607133 ] Reviewed-by: Marek Olšák <[email protected]>
* st/glx/xlib: check for null ctx pointer in glXIsDirect()Brian Paul2013-05-211-3/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64745 Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* scons: Don't force stabs debug format for Mingw.José Fonseca2013-05-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - recent gdb handles DWARF fine (tested both with version 7.1.90.20100730 from mingw-w64 project, and 7.5-1 from mingw project) - http://people.freedesktop.org/~jrfonseca/bfdhelp/ was updated to handle DWARF - stabs requires ugly hacks to prevent compilation failures - mixing stabs/dwarf prevents proper backtraces (which is inevitable, given that the MinGW C runtime is pre-built with DWARF) For example, without this change I get: (gdb) bt #0 _wassert (_Message=0xf925060 L"Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0xf60b488 L"llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:51 #1 0x0368996b in _assert (_Message=0x39d7ee4 "Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0x39d7e94 "llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:44 #2 0x00000004 in ?? () #3 0x00000004 in ?? () #4 0x0f60b488 in ?? () #5 0x00000000 in ?? () While with this change I get: (gdb) bt #0 _wassert (_Message=0xfb982e8 L"Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0xefbcb40 L"llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:51 #1 0x039c996b in _assert (_Message=0x3d17f24 "Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0x3d17ed4 "llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:44 #2 0x033111cc in getOperand (Num=4, this=<optimized out>) at llvm/include/llvm/CodeGen/SelectionDAGNodes.h:534 #3 getOperand (i=4, this=<optimized out>) at llvm/include/llvm/CodeGen/SelectionDAGNodes.h:779 #4 llvm::SelectionDAG::getNode (this=0xf00cb08, Opcode=79, DL=..., VT=..., N1=..., N2=...) at llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2859 #5 0x03377b20 in llvm::SelectionDAGBuilder::visitExtractElement (this=0xfb45028, I=...) at llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:2803 [...] Reviewed-by: Brian Paul <[email protected]>
* ilo: use BLT engine to copy between texturesChia-I Wu2013-05-211-1/+237
| | | | | | Emit XY_SRC_COPY_BLT to do the job. Since ETC1 textures cannot be mapped for reading, as is required by util_copy_resource_region, this fixes copying of ETC1 textures.
* ilo: use BLT engine to copy between buffersChia-I Wu2013-05-211-1/+142
| | | | | Emit (possibly multiple) SRC_COPY_BLT to copy between buffers of arbitrary sizes.
* ilo: refactor blitter_xy_color_blt()Chia-I Wu2013-05-211-48/+92
| | | | | Add gen6_XY_COLOR_BLT() and let blitter_xy_color_blt() call the function. Not sure if this path is still being hit by any application.
* ilo: replace cp hooks by cp owner and flush callbackChia-I Wu2013-05-216-253/+249
| | | | | | | | | | | | | | | The problem with cp hooks is that when we switch from 3D ring to 2D ring, and when there are active queries, we will emit 3D commands to 2D ring because the new-batch hook is called. This commit introduces the idea of cp owner. When the cp is flushed, or when another owner takes place, the current owner is notified, giving it a chance to emit whatever commands there need to be. With this mechanism, we can resume queries when the 3D pipeline owns the cp, and pause queries when it loses the cp. Ring switch will just work. As we still need to know when the cp bo is reallocated, a flush callback is added.
* ilo: harware contexts are only for the render ringChia-I Wu2013-05-215-8/+12
| | | | | The hardware context should not be passed for bo execution when the ring is not the render ring. Rename hw_ctx to render_ctx for clarity.
* ilo: update format mappingsChia-I Wu2013-05-211-14/+79
| | | | | Add more PIPE_FORMAT -> BRW_SURFACEFORMAT mappings, and update surface_format_info from i965.
* ilo: update headers from i965Chia-I Wu2013-05-215-54/+149
| | | | Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.
* r600g/llvm: fix cubemap lod/biasVincent Lejeune2013-05-201-0/+3
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* r600g/llvm: Fix texelFetchOffset-2DVincent Lejeune2013-05-201-0/+6
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* r600g/llvm: Fix cubearray textureSizeVincent Lejeune2013-05-203-0/+17
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* r600g/llvm: Factorize code loading from const buffer.Vincent Lejeune2013-05-201-27/+24
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* llvmpipe: enable z32s8x24 formatRoland Scheidegger2013-05-181-6/+0
| | | | | | | | Now that we can handle it both for sampling and as depth/stencil enable it. Passes nearly all additional piglit tests which are now performed, with two exceptions (one being a framebuffer blit which fails for all other formats including stencil too as we don't support stencil blits, the other reporting a unexpected GL error so doesn't look to be llvmpipe's fault).
* llvmpipe: handle z32s8x24 depth/stencil formatRoland Scheidegger2013-05-189-148/+259
| | | | | | | We need to split up the depth and stencil values in this case, and there's some new logic required to handle float depth and stencil simultaneously. Also make sure we get the 64bit zs clear values and masks propagated correctly.
* llvmpipe: get rid of unused tiled/linear logicRoland Scheidegger2013-05-187-713/+50
| | | | | | | | | We do rendering to linear color buffers for quite some time, and since switching to linear depth buffers all the tiled/linear logic was unused. So get rid of (most) of it - there's still some LAYOUT_NONE things and late allocation of resources which probably could be simplified. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix bogus handling of first_layer when setting up texture samplingRoland Scheidegger2013-05-182-14/+18
| | | | | | | | | | | | The code avoided first_layer parameter in the sampler interface (and needing to do another calculation at runtime) by fixing up the base texture pointer instead. Unfortunately, this didn't actually work as we have mip-first texture layout so fixing up the base ptr by a fixed amount is very wrong if there are mipmaps present. The wrong offsets caused misrendering and crashes. Fix this by just adjusting the individual mip level offsets instead. Spotted by Jose. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: handle z32s8x24 format for samplingRoland Scheidegger2013-05-181-8/+51
| | | | | | | | | | | | | | | Since we can only sample either depth or stencil but not both only load the required bits which makes things a bit easier (it requires special handling since the format doesn't fit into 32bit). The logic for deciding if depth or stencil should be sampled is a bit odd, but seems to be what other drivers and statetrackers do: if it's a format with both depth and stencil (or just with depth) then sample depth, for sampling stencil a sampler view format with only stencil is required. Also while here fix up stencil sampling for other formats as well, though this isn't supported by mesa (ARB_stencil_texturing), and while blits would use it they don't work neither since they'd also need stencil export. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.José Fonseca2013-05-175-242/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change was meant as a stepping stone to use PMADDUBSW SSSE3 instruction, but actually this refactoring by itself yields a 10% speedup on texture intensive shaders (e.g, Google Earth's ocean water w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the same results, whereas PMADDUBSW only gave an extra 5%, at the expense of 2bits of precision in the interpolation. I belive that the speedup of this change comes from the reduced register pressure (as 8.8 fixed point intermediates take twice the space of 8bit unorm). Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code substantially -- it's no longer necessary to have code duplicated for low and high register halfs. Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never executed (as it is faster on AVX to split the 256bit wide texture computation into two 128bit chunks, in order to leverage integer opcodes). This path might be useful in the future, so in order to verify this change did not break that path I had to apply this change: @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm, /* * we only try 8-wide sampling with soa as it appears to * be a loss with aos with AVX (but it should work). * (It should be faster if we'd support avx2) */ - if (num_quads == 1 || !use_aos) { + if (/* num_quads == 1 || ! */ use_aos) { if (num_quads > 1) { if (mip_filter == PIPE_TEX_MIPFILTER_NONE) { LLVMValueRef index0 = lp_build_const_int32(gallivm, 0); /* and then run texfilt mesademo: LP_NATIVE_VECTOR_WIDTH=256 ./texfilt Ran whole piglit without regressions. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Add and use lp_build_lerp_3d.José Fonseca2013-05-173-26/+60
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/llvm: Run standard optimization passes on conpute shader modulesTom Stellard2013-05-171-0/+15
| | | | | | The SROA and function inliner passes are espically important, because they optimize away unsupported features: functions and indirect private memory access.
* r600g: fixup for MSAA texture support checkingNiels Ole Salscheider2013-05-161-1/+1
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* llvmpipe: Temporary workaround to prevent segfault on array textures.José Fonseca2013-05-161-0/+3
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* gallivm: Support pointers in lp_build_print_value().José Fonseca2013-05-161-0/+2
| | | | Trivial.
* ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+Chia-I Wu2013-05-162-7/+21
| | | | | | Whether HiZ is enalbed or not, separate stencil is supported and enforced on GEN7+. Now that we support separate stencil resources, we know how to emit 3DSTATE_STENCIL_BUFFER.
* ilo: add support for stencil resources on GEN7+Chia-I Wu2013-05-168-33/+545
| | | | | | For allocations, we need to support stencil-only and separate stencil resources. For mapping, we need to support software tiling and packing/unpacking for separate stencil resources.
* winsys/intel: test for and expose address swizzlingChia-I Wu2013-05-162-0/+23
| | | | | Without knowing whether addresses are swizzled or not, we cannot manipulate a tiled surface in CPU.
* r600g: cleanup MSAA texture support checkingMarek Olšák2013-05-157-72/+21
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samplesMarek Olšák2013-05-157-36/+42
| | | | | | | | | | | | This fixes and enables texturing with compressed MSAA colorbuffers on Evergreen and Cayman. For the first time, multisample textures work on Cayman. This requires the libdrm flag RADEON_SURF_FMASK. v2: require libdrm_radeon 2.4.45 Reviewed-by: Alex Deucher <[email protected]>
* draw: More defensive coding in DRAW_GET_IDX.José Fonseca2013-05-151-2/+2
| | | | Doesn't make a difference ATM, but just in case.
* draw: Fix vsplit regression when the ib can be used directly.José Fonseca2013-05-151-1/+1
| | | | | | `ib` no longer is offseted by `istart`. Trivial.
* ilo: clean up transfer format conversionChia-I Wu2013-05-151-34/+48
| | | | Map the bo directly, instead of calling transfer_map().
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