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* gallium/radeon: handle buffer alloc failures in r600_draw_rectangleMarek Olšák2015-09-241-0/+3
* gallium/radeon: handle buffer_map staging buffer failures betterMarek Olšák2015-09-241-4/+3
* radeonsi: handle constant buffer alloc failuresMarek Olšák2015-09-241-1/+7
* radeonsi: handle index buffer alloc failuresMarek Olšák2015-09-241-0/+6
* st/xa: Fixups for PIPE_FORMAT_R8_UNORM A8 usage v2.Thomas Hellstrom2015-09-242-11/+29
* r600g: update num_dw in scissor_enable workaroundGrazvydas Ignotas2015-09-231-0/+1
* radeonsi: implement TXQS supportIlia Mirkin2015-09-212-25/+69
* radeonsi: load fmask ptr relative to the resources arrayIlia Mirkin2015-09-211-1/+1
* freedreno/ir3: use nir two-sided-color loweringRob Clark2015-09-181-21/+3
* freedreno/ir3: lower txp/clamp in NIRRob Clark2015-09-181-26/+30
* freedreno/ir3: add --gpu arg to cmdline compilerRob Clark2015-09-171-1/+10
* freedreno/a4xx: wire up ucp supportRob Clark2015-09-171-0/+1
* freedreno/ir3: add support for ucpRob Clark2015-09-174-13/+80
* freedreno/ir3: convert from tgsi semantic/index to varying-slotRob Clark2015-09-177-193/+234
* freedreno/ir3: switch to shader_enums.h interp constantsRob Clark2015-09-174-41/+20
* nv50,nvc0: flush texture cache in presence of coherent bufsIlia Mirkin2015-09-172-0/+39
* nv50,nvc0: detect underlying resource changes and update ticIlia Mirkin2015-09-172-0/+43
* vc4: Try to pair up instructions when only one of them has PM bitBoyan Ding2015-09-171-47/+76
* st/xa: Use PIPE_FORMAT_R8_UNORM when availableThomas Hellstrom2015-09-172-34/+34
* freedreno/a3xx: use NUM_USER_CLIP_PLANES helper instead of magic numberIlia Mirkin2015-09-161-1/+2
* freedreno/a3xx: fix blending of L8 formatIlia Mirkin2015-09-161-0/+2
* freedreno/a3xx: add support for dual-source blendingIlia Mirkin2015-09-167-6/+32
* vc4: convert from tgsi semantic/index to varying-slotEric Anholt2015-09-167-147/+106
* gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.Eric Anholt2015-09-166-47/+239
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
* freedreno: one screen to rule them allRob Clark2015-09-164-4/+125
* freedreno/ir3: use NIR to lower ffract instead of tgsi_loweringRob Clark2015-09-161-1/+1
* freedreno/a4xx: more texture formatsRob Clark2015-09-151-7/+8
* freedreno/a4xx: border-color supportRob Clark2015-09-154-2/+31
* freedreno/a4xx: wire up texture clamp loweringRob Clark2015-09-152-20/+80
* freedreno: helper for a3xx/a4xx border-colorsRob Clark2015-09-154-67/+99
* freedreno: update generated headersRob Clark2015-09-155-17/+37
* gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10Thomas Hellstrom2015-09-151-1/+1
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* vc4: Fix build from recent NIR cleanups.Eric Anholt2015-09-141-2/+1
* r600g: add support for TXQS tgsi opcodeIlia Mirkin2015-09-132-5/+13
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-135-9/+41
* gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supportedIlia Mirkin2015-09-1315-0/+15
* tgsi: add a TXQS opcode to retrieve the number of texture samplesIlia Mirkin2015-09-133-2/+14
* softpipe: Change faces type to uintKrzesimir Nowak2015-09-132-6/+6
* freedreno/ir3: fix compile warn after 1807a08eRob Clark2015-09-131-0/+1
* freedreno/ir3: fix compile break after a4aa25beRob Clark2015-09-131-2/+1
* tgsi/scan: add support to figure out max nesting depthRob Clark2015-09-132-0/+21
* r600: Fix llvm build since const buffer changesKai Wasserbäch2015-09-131-1/+1
* r600: Enable fp64 on chips with native supportGlenn Kennard2015-09-121-0/+3
* r600g: Support I2D/U2D/D2I/D2UGlenn Kennard2015-09-121-8/+98
* r600g: lower number of driver const buffersDave Airlie2015-09-123-70/+131
* r600: define some values for the fetch constant offsets.Dave Airlie2015-09-124-27/+47
* softpipe: Constify variablesKrzesimir Nowak2015-09-111-242/+199
* softpipe: Constify sp_tgsi_samplerKrzesimir Nowak2015-09-111-12/+23
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