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* ilo: update format mappingsChia-I Wu2013-05-211-14/+79
| | | | | Add more PIPE_FORMAT -> BRW_SURFACEFORMAT mappings, and update surface_format_info from i965.
* ilo: update headers from i965Chia-I Wu2013-05-215-54/+149
| | | | Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.
* r600g/llvm: fix cubemap lod/biasVincent Lejeune2013-05-201-0/+3
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* r600g/llvm: Fix texelFetchOffset-2DVincent Lejeune2013-05-201-0/+6
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* r600g/llvm: Fix cubearray textureSizeVincent Lejeune2013-05-203-0/+17
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* r600g/llvm: Factorize code loading from const buffer.Vincent Lejeune2013-05-201-27/+24
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* llvmpipe: enable z32s8x24 formatRoland Scheidegger2013-05-181-6/+0
| | | | | | | | Now that we can handle it both for sampling and as depth/stencil enable it. Passes nearly all additional piglit tests which are now performed, with two exceptions (one being a framebuffer blit which fails for all other formats including stencil too as we don't support stencil blits, the other reporting a unexpected GL error so doesn't look to be llvmpipe's fault).
* llvmpipe: handle z32s8x24 depth/stencil formatRoland Scheidegger2013-05-189-148/+259
| | | | | | | We need to split up the depth and stencil values in this case, and there's some new logic required to handle float depth and stencil simultaneously. Also make sure we get the 64bit zs clear values and masks propagated correctly.
* llvmpipe: get rid of unused tiled/linear logicRoland Scheidegger2013-05-187-713/+50
| | | | | | | | | We do rendering to linear color buffers for quite some time, and since switching to linear depth buffers all the tiled/linear logic was unused. So get rid of (most) of it - there's still some LAYOUT_NONE things and late allocation of resources which probably could be simplified. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix bogus handling of first_layer when setting up texture samplingRoland Scheidegger2013-05-182-14/+18
| | | | | | | | | | | | The code avoided first_layer parameter in the sampler interface (and needing to do another calculation at runtime) by fixing up the base texture pointer instead. Unfortunately, this didn't actually work as we have mip-first texture layout so fixing up the base ptr by a fixed amount is very wrong if there are mipmaps present. The wrong offsets caused misrendering and crashes. Fix this by just adjusting the individual mip level offsets instead. Spotted by Jose. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: handle z32s8x24 format for samplingRoland Scheidegger2013-05-181-8/+51
| | | | | | | | | | | | | | | Since we can only sample either depth or stencil but not both only load the required bits which makes things a bit easier (it requires special handling since the format doesn't fit into 32bit). The logic for deciding if depth or stencil should be sampled is a bit odd, but seems to be what other drivers and statetrackers do: if it's a format with both depth and stencil (or just with depth) then sample depth, for sampling stencil a sampler view format with only stencil is required. Also while here fix up stencil sampling for other formats as well, though this isn't supported by mesa (ARB_stencil_texturing), and while blits would use it they don't work neither since they'd also need stencil export. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.José Fonseca2013-05-175-242/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change was meant as a stepping stone to use PMADDUBSW SSSE3 instruction, but actually this refactoring by itself yields a 10% speedup on texture intensive shaders (e.g, Google Earth's ocean water w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the same results, whereas PMADDUBSW only gave an extra 5%, at the expense of 2bits of precision in the interpolation. I belive that the speedup of this change comes from the reduced register pressure (as 8.8 fixed point intermediates take twice the space of 8bit unorm). Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code substantially -- it's no longer necessary to have code duplicated for low and high register halfs. Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never executed (as it is faster on AVX to split the 256bit wide texture computation into two 128bit chunks, in order to leverage integer opcodes). This path might be useful in the future, so in order to verify this change did not break that path I had to apply this change: @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm, /* * we only try 8-wide sampling with soa as it appears to * be a loss with aos with AVX (but it should work). * (It should be faster if we'd support avx2) */ - if (num_quads == 1 || !use_aos) { + if (/* num_quads == 1 || ! */ use_aos) { if (num_quads > 1) { if (mip_filter == PIPE_TEX_MIPFILTER_NONE) { LLVMValueRef index0 = lp_build_const_int32(gallivm, 0); /* and then run texfilt mesademo: LP_NATIVE_VECTOR_WIDTH=256 ./texfilt Ran whole piglit without regressions. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Add and use lp_build_lerp_3d.José Fonseca2013-05-173-26/+60
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/llvm: Run standard optimization passes on conpute shader modulesTom Stellard2013-05-171-0/+15
| | | | | | The SROA and function inliner passes are espically important, because they optimize away unsupported features: functions and indirect private memory access.
* r600g: fixup for MSAA texture support checkingNiels Ole Salscheider2013-05-161-1/+1
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* llvmpipe: Temporary workaround to prevent segfault on array textures.José Fonseca2013-05-161-0/+3
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* gallivm: Support pointers in lp_build_print_value().José Fonseca2013-05-161-0/+2
| | | | Trivial.
* ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+Chia-I Wu2013-05-162-7/+21
| | | | | | Whether HiZ is enalbed or not, separate stencil is supported and enforced on GEN7+. Now that we support separate stencil resources, we know how to emit 3DSTATE_STENCIL_BUFFER.
* ilo: add support for stencil resources on GEN7+Chia-I Wu2013-05-168-33/+545
| | | | | | For allocations, we need to support stencil-only and separate stencil resources. For mapping, we need to support software tiling and packing/unpacking for separate stencil resources.
* winsys/intel: test for and expose address swizzlingChia-I Wu2013-05-162-0/+23
| | | | | Without knowing whether addresses are swizzled or not, we cannot manipulate a tiled surface in CPU.
* r600g: cleanup MSAA texture support checkingMarek Olšák2013-05-157-72/+21
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samplesMarek Olšák2013-05-157-36/+42
| | | | | | | | | | | | This fixes and enables texturing with compressed MSAA colorbuffers on Evergreen and Cayman. For the first time, multisample textures work on Cayman. This requires the libdrm flag RADEON_SURF_FMASK. v2: require libdrm_radeon 2.4.45 Reviewed-by: Alex Deucher <[email protected]>
* draw: More defensive coding in DRAW_GET_IDX.José Fonseca2013-05-151-2/+2
| | | | Doesn't make a difference ATM, but just in case.
* draw: Fix vsplit regression when the ib can be used directly.José Fonseca2013-05-151-1/+1
| | | | | | `ib` no longer is offseted by `istart`. Trivial.
* ilo: clean up transfer format conversionChia-I Wu2013-05-151-34/+48
| | | | Map the bo directly, instead of calling transfer_map().
* ilo: rework transfer mapping method choosingChia-I Wu2013-05-151-102/+133
| | | | | | Always check if a bo is busy in choose_transfer_method() since we always need to map it in either map() or unmap(). Also determine how a bo is mapped in choose_transfer_method().
* ilo: refactor transfer mappingChia-I Wu2013-05-151-27/+52
| | | | | Add tex_get_box_offset() to compute transfer offet from the pipe_box. Add tex_get_slice_stride() to compute slice stride for a transfer.
* ilo: no writeback without PIPE_TRANSFER_WRITEChia-I Wu2013-05-151-0/+5
| | | | We should not write staging data back when PIPE_TRANSFER_WRITE is not set.
* ilo: minor cleanups for transfersChia-I Wu2013-05-151-41/+41
| | | | Rename some functions and reorder some code.
* ilo: simplify ilo_texture_get_slice_offset()Chia-I Wu2013-05-154-55/+40
| | | | Always return a tile-aligned offset. Also fix for W tiling.
* draw/gs: fix extracting of the clipZack Rusin2013-05-141-2/+4
| | | | | | | | | | The indices are not consecutive when using the geometry shader, which means we were extracting non existing values. Create an array of linear indices and always use it instead of the passed indices. Found by Jose. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* draw: try to prevent overflows on index buffersZack Rusin2013-05-1414-68/+137
| | | | | | | | | | | | Pass in the size of the index buffer, when available, and use it to handle out of bounds conditions. The behavior in the case of an overflow needs to be the same as with other overflows in the vertex processing pipeline meaning that a vertex should still be generated but all attributes in it set to zero. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw: use the total number of vertices for statisticsZack Rusin2013-05-142-2/+2
| | | | | | | | | | | the number of vertices to fetch doesn't necessarily equal the total number of input vertices, e.g. we might want to fetch a single vertex but then draw it twice. Lets use the correct number of input vertices in the statistics. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw: don't crash on vertex buffer overflowZack Rusin2013-05-1416-42/+137
| | | | | | | | | | | | | | We would crash when stride was bigger than the size of the buffer. The correct behavior is to just fetch zero's in this case. Unfortunatly with user_buffer's there's no way to validate the size because currently we're just not getting it. Adjust the draw interface to pass the size along the mapped buffer, which works perfectly for buffer backed vertex_buffers and, in future, it will allow us to plumb user_buffer sizes through the same interface. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm/soa: implement indirect addressing in immediatesZack Rusin2013-05-142-2/+82
| | | | | | | | | | | | | The support is analogous to the way we handle indirect addressing in temporaries, except that we don't have to worry about storing (after declarations) and thus we'll able to keep using the old code when indirect addressing isn't used. In other words we're still using constants directly, unless the instruction has immediate register with indirect addressing. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw/gs: don't bind the tgsi state if we're using llvm pathsZack Rusin2013-05-141-1/+6
| | | | | | Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Fix build with LLVM >= 3.4 r181680.Vinson Lee2013-05-141-1/+3
| | | | | Tested-by: Laurent Carlier <[email protected]> Signed-off-by: Vinson Lee <[email protected]>
* radeonsi: update r600_get_llvm_processor_name for hainanAlex Deucher2013-05-141-0/+1
| | | | | Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for hainan chipsAlex Deucher2013-05-144-0/+6
| | | | | | | Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* draw: Fix io_ptr/num_prims name in IR.José Fonseca2013-05-141-1/+1
| | | | Trivial.
* graw/tgsi_dump: Fix gdb macro.José Fonseca2013-05-141-2/+2
| | | | The macro was relying on "tokens" local variable to exist.
* r600g/sb: add missing cases for ARUBA chipsVadim Girlin2013-05-142-0/+2
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: get rid of standard c++ streamsVadim Girlin2013-05-1424-545/+592
| | | | | | | | | | | | Static initialization of internal libstdc++ data related to iostream causes segfaults with some apps. This patch replaces all uses of std::ostream and std::ostringstream in sb with custom lightweight classes. Prevents segfaults with ut2004demo and probably some other old apps. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: separate bytecode decoding and parsingVadim Girlin2013-05-146-144/+163
| | | | | | | | | Parsing and ir construction is required for optimization only, it's unnecessary if we only need to print shader dump. This should make new disassembler more tolerant to any new features in the bytecode. Signed-off-by: Vadim Girlin <[email protected]>
* vl/vdpau: fix PresentationQueueQuerySurfaceStatusChristian König2013-05-142-17/+19
| | | | | | | | The last queued surface always keeps displaying. Fixing a problem with XBMC. Signed-off-by: Christian König <[email protected]>
* ilo: rework ilo_textureChia-I Wu2013-05-145-766/+1027
| | | | | Use ilo_buffer for buffer resources and ilo_texture for texture resources. A major cleanup is necessitated by the separation.
* ilo: rename ilo_resource to ilo_textureChia-I Wu2013-05-147-322/+322
| | | | In preparation for the introduction of ilo_buffer.
* ilo: move transfer-related functions to a new fileChia-I Wu2013-05-146-450/+518
| | | | | | Resource mapping is distinct from resource allocation, and is going to get more and more complex. Move the related functions to a new file to make the separation clear.
* gallium: add PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE for GLMarek Olšák2013-05-1111-1/+19
| | | | | | v2: fix typo 65535 -> 65536 Reviewed-by: Brian Paul <[email protected]>
* ilo: Initialize read_back in transfer_map_sys.Vinson Lee2013-05-101-1/+1
| | | | | | | Fixes "Uninitialized scalar variable" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
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