summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Collapse)AuthorAgeFilesLines
* cso: put cso_release_all into cso_destroy_contextMarek Olšák2014-12-108-32/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/target: Haiku softpipeAlexander von Gluck IV2014-12-101-1/+1
| | | | * Use print macro to fix warning on 64-bit systems
* gallium/aux: Avoid redefining MAXAlexander von Gluck IV2014-12-101-0/+2
| | | | * Can be redefined on some platforms through u_debug.h
* clover: Use switch when creating kernel arguments.Jan Vesely2014-12-101-25/+19
| | | | | | | | | This way we get a warning if an enum value is not handled. v2: codestyle Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* r600g: only init GS_VERT_ITEMSIZE on r600Dave Airlie2014-12-101-5/+2
| | | | | | | | | | | | On evergreen there are 4 regs, on r600/700 there is only one. Don't initialise regs and trash someone elses state. Not sure this fixes anything, but hey one less stupid. Reviewed-By: Glenn Kennard <[email protected]> Cc: "10.3 10.4" [email protected] Signed-off-by: Dave Airlie <[email protected]>
* vc4: Do QPU scheduling across uniform loads.Eric Anholt2014-12-091-28/+60
| | | | | | | | This means another pass of reordering the uniform data store, but it lets us pair up a lot more instructions. total instructions in shared programs: 44639 -> 43176 (-3.28%) instructions in affected programs: 36938 -> 35475 (-3.96%)
* vc4: Populate the delay field better, and schedule high delay first.Eric Anholt2014-12-091-1/+49
| | | | | | | This is a standard scheduling heuristic, and clearly helps. total instructions in shared programs: 46418 -> 44467 (-4.20%) instructions in affected programs: 42531 -> 40580 (-4.59%)
* vc4: Skip raddr dependencies for 32-bit immediate loads.Eric Anholt2014-12-091-2/+5
| | | | These don't have raddr fields.
* vc4: Mark VPM read setup as impacting VPM reads, not writes.Eric Anholt2014-12-091-1/+7
| | | | | Fixes assertion failures if we adjust scheduling priorities to emphasize VPM reads more.
* vc4: Refuse to merge instructions involving 32-bit immediate loads.Eric Anholt2014-12-091-0/+5
| | | | | An immediate load overwrites the mul and add operations, so you can't merge with them.
* clover: Fix build after llvm r223802Aaron Watry2014-12-091-0/+4
| | | | | Signed-off-by: Aaron Watry <awatry at gmail.com> Reviewed-by: Tom Stellard <[email protected]>
* freedreno/a4xx: frag-coord / face fixesRob Clark2014-12-091-6/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix rendering to layer != 0Rob Clark2014-12-091-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: temp hack for FLAT varyingsRob Clark2014-12-091-0/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower TXP as neededRob Clark2014-12-093-3/+19
| | | | | | On a3xx, lower TXP for 3D textures, on a4xx lower all TXP. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: XA gpu hang at startupRob Clark2014-12-092-1/+9
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: texture fixesRob Clark2014-12-096-7/+54
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: cleanup slice alignment/setupRob Clark2014-12-091-36/+14
| | | | | | | | Collapse things back into a setup_slices() which takes the desired alignment as a param. This gets things ready for a4xx which has some slightly different requirements. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-096-18/+65
| | | | Signed-off-by: Rob Clark <[email protected]>
* tgsi/lowering: add support to lower TXP (v2)Rob Clark2014-12-092-15/+34
| | | | | | | v2: actually do perspective divide for RECT/SHADOWRECT Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* draw: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITIONMarek Olšák2014-12-0910-11/+49
| | | | | | | Required by Nine. Tested with util_run_tests. It's added to softpipe, llvmpipe, and r300g/swtcl. Tested-by: David Heidelberg <[email protected]>
* vc4: Reserve rb31 instead of r3 for raddr conflict spills.Eric Anholt2014-12-092-11/+45
| | | | | | | | | | This increases the cost of a raddr b conflict spill (save r3 to rb31, move src1 to r3, move rb31 back to r3 when done, instead of just move src1 to r3), but on average thanks to instruction pairing it's more worthwhile to have another accumulator. total instructions in shared programs: 46428 -> 46171 (-0.55%) instructions in affected programs: 38030 -> 37773 (-0.68%)
* vc4: Prioritize allocating accumulators to short-lived values.Eric Anholt2014-12-091-14/+59
| | | | | | | | | | | | | | | | | | The register allocator walks from the end of the nodes array looking for trivially-allocatable things to put on the stack, meaning (assuming everything is trivially colorable and gets put on the stack in a single pass) the low node numbers get allocated first. The things allocated first happen to get the lower-numbered registers, which is to say the fast accumulators that can be paired more easily. When we previously made the nodes match the temporary register numbers, we'd end up putting the shader inputs (VS or FS) in the accumulators, which are often long-lived values. By prioritizing the shortest-lived values for allocation, we can get a lot more instructions that involve accumulators, and thus fewer conflicts for raddr and WS. total instructions in shared programs: 52870 -> 46428 (-12.18%) instructions in affected programs: 52260 -> 45818 (-12.33%)
* r600g: fix regression since UCMP changeDave Airlie2014-12-091-1/+1
| | | | | | | | | | | | Since d8da6deceadf5e48201d848b7061dad17a5b7cac where the state tracker started using UCMP on cayman a number of tests regressed. this seems to be r600g is doing CNDGE_INT for UCMP which is >= 0, we should be doing CNDE_INT with reverse arguments. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2014-12-084-10/+8
| | | | | | | See commit 2b7a972e for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2014-12-0818-65/+36
| | | | | | | See commits 5067506e and b6109de3 for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: Interleave register allocation from regfile A and B.Eric Anholt2014-12-081-39/+38
| | | | | | | | | | | | | The register allocator prefers low-index registers from vc4_regs[] in the configuration we're using, which is good because it means we prioritize allocating the accumulators (which are faster). On the other hand, it was causing raddr conflicts because everything beyond r0-r2 ended up in regfile A until you got massive register pressure. By interleaving, we end up getting more instruction pairing from getting non-conflicting raddrs and QPU_WSes. total instructions in shared programs: 55957 -> 52719 (-5.79%) instructions in affected programs: 46855 -> 43617 (-6.91%)
* vc4: Fix decision for whether the MIN operation writes to the B regfile.Eric Anholt2014-12-081-3/+3
|
* vc4: Drop dependency on r3 for color packing.Eric Anholt2014-12-081-4/+27
| | | | | | | | We can avoid it by carefully ordering the packing. This is important as a step in giving r3 to the register allocator. total instructions in shared programs: 56087 -> 55957 (-0.23%) instructions in affected programs: 18368 -> 18238 (-0.71%)
* vc4: Add support for GL 1.0 logic ops.Eric Anholt2014-12-081-2/+60
|
* vc4: Add support for TGSI_OPCODE_UCMP.Eric Anholt2014-12-081-0/+12
| | | | This is being emitted now from st_glsl_to_tgsi.cpp.
* radeonsi/compute: Clamp COMPUTE_TMPRING_SIZE.WAVES to: num_cu * 32Tom Stellard2014-12-081-0/+3
| | | | This is the maximum value allowed for this field.
* winsys/radeon: Always report at least 1 compute unitTom Stellard2014-12-082-1/+3
| | | | | | | | All uses of this require that the value be at least one, so it's easier to report at least one than having to wrap all uses in MAX2(max_compute_units, 1). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Program RASTER_CONFIG for harvested GPUs v5Tom Stellard2014-12-084-6/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Harvested GPUs have some of their render backends disabled, so in order to prevent the hardware from trying to render things with these disabled backends we need to correctly program the PA_SC_RASTER_CONFIG register. v2: - Write RASTER_CONFIG for all SEs. v3: - Set GRBM_GFX_INDEX.INSTANCE_BROADCAST_WRITES bit. - Set GRBM_GFX_INFEX.SH_BROADCAST_WRITES bit when done setting PA_SC_RASTER_CONFIG. - Get num_se and num_sh_per_se from kernel. v4: - Get correct value for num_se - Remove loop for setting PA_SC_RASTER_CONFIG - Only compute raster config when a backend has been disabled. v5: Michel Dänzer - Fix computation for chips with multiple SEs https://bugs.freedesktop.org/show_bug.cgi?id=60879 CC: "10.4 10.3" <[email protected]>
* draw: (trivial): remove double semicolonRoland Scheidegger2014-12-091-1/+1
|
* freedreno/a2xx: silence warning about missing DEPTH32XIlia Mirkin2014-12-061-1/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle index_bias (i.e. base_vertex)Ilia Mirkin2014-12-061-3/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add bgr565 texturing and renderingIlia Mirkin2014-12-061-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add support for SRGB render targetsIlia Mirkin2014-12-062-9/+12
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputsIlia Mirkin2014-12-063-1/+17
| | | | | | | Fixes R11G11B10F rendering, and is required for SRGB format support. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: re-enable rgb10_a2 render targetsIlia Mirkin2014-12-061-1/+3
| | | | | | | | There were previously regressions regarding border colors, which the updated swizzle logic resolves. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix border color swizzle to match texture format descIlia Mirkin2014-12-061-4/+18
| | | | | | | | | This is a hack since it uses the texture information together with the sampler, but I don't see a better way to do it. In OpenGL, there is a 1:1 correspondence. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix alpha-blending on RGBX formatsIlia Mirkin2014-12-065-8/+55
| | | | | | | Expert debugging assistance provided by Chris Forbes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* llvmpipe: decrease MAX_SCENES from 2 to 1Roland Scheidegger2014-12-062-1/+13
| | | | | | | | | | | | | | | | | | Multiple scenes per context are meant to be used so a new scene can be built while another one is processed in rasterization. However, quite surprisingly, this does not actually work (and according to git log, possibly never did, though maybe it did at some point further back (5 years+) but was buggy) because we always wait immediately on the rasterizer to finish the scene when contexts (and hence setup/scene) is flushed. This means when we try to get an empty scene later, any old one is already empty again. Thus using multiple scenes is just a waste of memory (not too bad, since the additional scenes are guaranteed to be empty, which means their size ought to be one data block (64kB) plus the size of some structs), without actually really doing anything. (There is also quite some code for the whole concept of multiple scenes which doesn't really do much in practice, but keep it hoping the wait-on-scene-flush can be fixed some day.) Reviewed-by: Jose Fonseca <[email protected]>
* draw: use the prim type from prim_info not emit in passthrough emitRoland Scheidegger2014-12-061-2/+2
| | | | | | | | | | | | The prim assembler may change the prim type when injecting prim ids now, which isn't reflected by what's stored in emit. This looks brittle and potentially dangerous (it is not obvious if such prim type changes are really supported by pt emit, the prim type is actually also set in prepare which would then be different). This fixes piglit primitive-id-no-gs-first-vertex.shader_test. Reviewed-by: Jose Fonseca <[email protected]>
* draw: use correct output prim for non-adjacent topologies in prim assembler.Roland Scheidegger2014-12-061-4/+4
| | | | | | | | | | | | | | | | | The decomposition done in the prim assembler will turn tri fans into tris, but this wasn't reflected in the output prim type. Meaning with a tri fan with 6 verts input, the output was a tri fan with 12 vertices instead of a tri list with 12 vertices (not as bad as it sounds, since the additional tris created would all be degenerate since they'd all have two times vertex zero but still bogus). This is because the prim assembler is used if either the input topology is something with adjacency, or if prim id needs to be injected, and for the latter case topologies without adjacency can be converted to basic ones. Unfortunately decomposition here for inserting prim ids is necessary, at least for the indexed case where we can't just insert the prim id at the right place depending on provoking vertex. Reviewed-by: Jose Fonseca <[email protected]>
* draw: kill off unneded prim assembler code for handling adjacency vertsRoland Scheidegger2014-12-062-60/+0
| | | | | | | | The default macros when the adjacency macros aren't defined will already exactly do that (that is, drop the adjacent vertices and call the non-adjacent macro). Reviewed-by: Jose Fonseca <[email protected]>
* gallium/docs: (trivial) remove STR opcode description.Roland Scheidegger2014-12-061-9/+0
| | | | | The opcode was removed alongside SFL by commit ecfe9e2ad2b5f178ef09420f8d95d49937137cd9.
* vc4: Try swapping the regfile A to B to pair instructions.Eric Anholt2014-12-051-2/+62
| | | | | total instructions in shared programs: 56995 -> 56087 (-1.59%) instructions in affected programs: 40503 -> 39595 (-2.24%)
* vc4: Allow pairing of some instructions that disagree about the WS bit.Eric Anholt2014-12-051-1/+47
| | | | | No difference on shader-db because we tend to have a lot of other conflicts going on as well (like RADDR_A disagreements)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 08:02:06 +0000