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gallium
Commit message (
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Author
Age
Files
Lines
*
gallium: Add blending to pipe blit
Christoph Bumiller
2015-08-21
3
-0
/
+4
*
st/nine: Revert to sw cursor in case of failure to set hw cursor
Axel Davy
2015-08-21
1
-2
/
+2
*
st/nine: Do not call ID3DPresent_GetCursorPos for sw cursor
Axel Davy
2015-08-21
1
-3
/
+4
*
st/nine: Force hw cursor for Windowed mode
Axel Davy
2015-08-21
1
-3
/
+9
*
st/nine: Hide hardware cursor when we don't use it
Axel Davy
2015-08-21
1
-6
/
+12
*
st/nine: fix D3DRS_DITHERENABLE wrong state group
Axel Davy
2015-08-21
1
-1
/
+1
*
st/nine: Account POINTSIZE_MIN and POINTSIZE_MAX for point size
Patrick Rudolph
2015-08-21
3
-14
/
+19
*
st/nine: Align texture memory
Patrick Rudolph
2015-08-21
4
-6
/
+6
*
st/nine: Always set point_quad_rasterization to 1
Axel Davy
2015-08-21
1
-1
/
+1
*
st/nine: Fix Swizzle for ATI2 format
Axel Davy
2015-08-21
1
-0
/
+5
*
target/d3dadapter9: Return Windows like card names
Patrick Rudolph
2015-08-21
3
-42
/
+359
*
clover: fix llvm 3.5 build error
Zoltan Gilian
2015-08-21
1
-12
/
+21
*
vc4: Add algebraic opt for rcp(1.0).
Eric Anholt
2015-08-20
1
-0
/
+8
*
vc4: Allow unpack_8[abcd]_f's src to stay in r4.
Eric Anholt
2015-08-20
1
-1
/
+15
*
vc4: Pack the unorm-packing bits into a src MUL instruction when possible.
Eric Anholt
2015-08-20
5
-16
/
+104
*
vc4: Add a QIR helper for whether the op is a MUL type.
Eric Anholt
2015-08-20
3
-4
/
+16
*
vc4: Drop an unused algebraic op.
Eric Anholt
2015-08-20
1
-9
/
+0
*
vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.
Eric Anholt
2015-08-20
5
-21
/
+19
*
vc4: Make the pack-to-unorm instructions be non-SSA.
Eric Anholt
2015-08-20
4
-42
/
+36
*
vc4: Allow QIR registers to be non-SSA.
Eric Anholt
2015-08-20
4
-4
/
+10
*
vc4: We can now move TEX_RESULT accesses across other r4 ops.
Eric Anholt
2015-08-20
1
-16
/
+0
*
nv50/ir: pre-compute BFE arg when both bits and offset are imm
Ilia Mirkin
2015-08-20
1
-3
/
+9
*
r600g: Fix handling of TGSI_OPCODE_ARR with SB
Glenn Kennard
2015-08-21
1
-1
/
+1
*
r600: Turn 'r600_shader_key' struct into union
Edward O'Callaghan
2015-08-21
4
-38
/
+42
*
r600: Rewrite r600_shader_selector_key() to use a switch stmt
Edward O'Callaghan
2015-08-21
1
-7
/
+17
*
nv50/ir: Handle OP_CVT when folding constant expressions
Tobias Klausmann
2015-08-20
1
-0
/
+78
*
nvc0/ir: undo more shifts still by allowing a pre-SHL to occur
Ilia Mirkin
2015-08-20
1
-15
/
+33
*
nvc0/ir: don't require AND when the high byte is being addressed
Ilia Mirkin
2015-08-20
1
-0
/
+12
*
nvc0/ir: detect i2f/i2i which operate on specific bytes/words
Ilia Mirkin
2015-08-20
4
-4
/
+82
*
nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Ilia Mirkin
2015-08-20
1
-20
/
+46
*
nv50/ir: support different unordered_set implementations
Chih-Wei Huang
2015-08-20
5
-12
/
+57
*
radeonsi: fix a typo as_es -> as_ls in a string
Marek Olšák
2015-08-19
1
-1
/
+1
*
winsys/amdgpu: fix the type of memory usage counters
Marek Olšák
2015-08-19
1
-2
/
+2
*
radeonsi: fix indirect indexing of MSAA textures
Marek Olšák
2015-08-19
1
-4
/
+13
*
util/ra: Make allocating conflict lists optional
Jason Ekstrand
2015-08-18
3
-3
/
+4
*
freedreno: use fd_pipe_wait_timeout()
Rob Clark
2015-08-18
2
-21
/
+1
*
freedreno: fence fix
Rob Clark
2015-08-18
3
-4
/
+8
*
Add mesa.icd to the .gitignore
Neil Roberts
2015-08-18
1
-0
/
+1
*
radeon/uvd: remove unused variables
Grazvydas Ignotas
2015-08-18
1
-4
/
+1
*
nouveau: recognize tess stages in nouveau_compiler
Marcos Paulo de Souza
2015-08-17
1
-0
/
+4
*
tgsi: fix parsing of tessellation shader inputs/outputs
Marcos Paulo de Souza
2015-08-17
1
-1
/
+16
*
tgsi: set implicit array size for tess stages
Marcos Paulo de Souza
2015-08-17
1
-1
/
+5
*
freedreno/a3xx: add s3tc texture format support
Ilia Mirkin
2015-08-17
1
-0
/
+9
*
freedreno/a3xx: fix up logic for handling block formats
Ilia Mirkin
2015-08-17
3
-5
/
+7
*
freedreno/a3xx: double the polygon offset value
Ilia Mirkin
2015-08-17
1
-1
/
+1
*
nvc0: implement the color buffer 0 is integer rule for alpha-to-one/cov
Ilia Mirkin
2015-08-17
3
-11
/
+22
*
gk110/ir: fix sched calculator to consider all registers in the ISA
Ilia Mirkin
2015-08-17
1
-7
/
+10
*
nvc0: program smooth line width when multisampling is enabled
Ilia Mirkin
2015-08-17
1
-1
/
+1
*
nvc0: bind a fake tess control program when there isn't one available
Ilia Mirkin
2015-08-17
4
-8
/
+44
*
gm107/ir: avoid letting the lowering pass get out of sync
Ilia Mirkin
2015-08-17
2
-88
/
+5
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