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* winsys/radeon: don't call surface_best for FMASKMarek Olšák2016-11-051-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98518 Acked-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: Multiply bpe by nsamples in surf_winsys_to_drmMichel Dänzer2016-11-041-2/+5
| | | | | | | For symmetry with surf_drm_to_winsys. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: Use flags parameter in radeon_winsys_surface_initMichel Dänzer2016-11-041-1/+1
| | | | | | | Fixes valgrind warnings about surf_ws->flags being uninitialized while starting X. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is setMichel Dänzer2016-11-041-10/+21
| | | | | | | Fixes valgrind warnings about using uninitialized memory when starting X. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: Only loop up to last_level for drm<->winsys conversionMichel Dänzer2016-11-041-2/+2
| | | | | | | | | Fixes spurious assertion failure in surf_level_drm_to_winsys when starting X, due to processing a miplevel which was never initialized. Fixes: e9c76eeeaa67 ("gallium/radeon: remove radeon_surf_level::pitch_bytes") Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add radeon_surf::is_linearMarek Olšák2016-11-012-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove radeon_surf_level::pitch_bytesMarek Olšák2016-11-012-9/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: replace radeon_surf_info::dcc_enabled with num_dcc_levelsMarek Olšák2016-11-011-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't force the same tiling parameters for FMASKMarek Olšák2016-10-261-0/+2
| | | | | | | | | GCN can use a completely different tile mode for FMASK. FMASK allocation now skips one unrelated amdgpu_surface_init codepath as hinted by the assertion. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: allocate FMASK properlyMarek Olšák2016-10-261-2/+4
| | | | | | | I expect no change in behavior, because r600_texture.c forces the same tile mode as the base texture has. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignmentMarek Olšák2016-10-262-9/+9
| | | | | | these names were misleading. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove flags specific to libdrm_radeon from winsys interfaceMarek Olšák2016-10-261-1/+3
| | | | | | | These just say whether libdrm can assume that the latest radeon_surface definition is used by Mesa. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove unnecessary fields from radeon_surf_levelMarek Olšák2016-10-262-15/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: decrease the size of radeon_surfMarek Olšák2016-10-261-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: pass pipe_resource and other params to surface_init directlyMarek Olšák2016-10-262-91/+128
| | | | | | | | | This removes input-only parameters from the radeon_surf structure. Some of the translation logic from pipe_resource to radeon_surf is moved to winsys/radeon. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: remove unused definitionsMarek Olšák2016-10-261-8/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fold radeon_winsys::surface_best into radeon/winsysMarek Olšák2016-10-262-25/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: fix radeon_surf::macro_tile_index for imported texturesMarek Olšák2016-10-261-0/+17
| | | | | | | | | | | | | | | Maybe this is why SDMA has been broken for many amdgpu users? SDMA is the only block which is used with imported textures and relies on this variable. DB also uses it, but it doesn't get imported textures, so it's unaffected. I do get SDMA failures on Tonga before this patch if R600_DEBUG=testdma is changed to use imported textures. Cc: 11.2 12.0 13.0 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-131-4/+53
| | | | | | | | | | | | | | | | | | | | | so that decompress blits aren't needed and depth texturing needs less memory bandwidth. Z16 and Z24 are promoted to Z32_FLOAT by the driver, because TC-compatible HTILE only supports Z32_FLOAT. This doubles memory footprint for Z16. The format promotion is not visible to state trackers. This is part of TC-compatible renderbuffer compression, which has 3 parts: DCC, HTILE, FMASK. Only TC-compatible FMASK compression is missing now. I don't see a measurable increase in performance though. (I tested Talos Principle and DiRT: Showdown, the latter is improved by 0.5%, which is almost noise, and it originally used layered Z16, so at least we know that Z16 promoted to Z32F isn't slower now) Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: fix infinite loop w/ RADEON_NOOP=1 caused by unsubmitted fencesMarek Olšák2016-10-121-2/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: set reasonable max_alloc_sizeMarek Olšák2016-10-052-3/+5
| | | | | | | | | | which is returned for GL_MAX_TEXTURE_BUFFER_SIZE. It doesn't have any other use at the moment. Bigger allocations are not rejected. This fixes GL45-CTS.texture_buffer.texture_buffer_max_size on Bonaire. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: add buffer_get_reloc_offsetNicolai Hähnle2016-10-041-0/+11
| | | | | | | | | | | Really fix the bug that was supposed to be fixed by commits 3e7cced4b and a48bf02d: even when virtual addresses are used, the legacy relocation-based method with offsets relative to the kernel's buffer object are used for video submissions. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969 Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)Matt Whitlock2016-10-045-5/+9
| | | | | | | | | | Without this fix, duplicated file descriptors leak into child processes. See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance where the same fix was employed. Cc: <[email protected]> Signed-off-by: Matt Whitlock <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: add radeon_winsys::min_alloc_sizeNicolai Hähnle2016-09-292-0/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon/winsyses: reduce the number of pb_cache bucketsNicolai Hähnle2016-09-272-8/+4
| | | | | | | Small buffers are now handled via the slabs code, so separate buckets in pb_cache have become redundant. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: enable buffer allocation from slabsNicolai Hähnle2016-09-274-2/+209
| | | | | | | Only enable for chips with GPUVM, because older driver paths do not take the required offset into account. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add fine-grained fences for slab buffersNicolai Hähnle2016-09-275-11/+137
| | | | | | | | | | | | | | | Note the logic for adding fences is somewhat different than for amdgpu, because radeon has no scheduler and we therefore have no guarantee about the order in which submissions from multiple threads are processed. (Ironically, this is only an issue when "multi-threaded submission" is disabled, because "multi-threaded submission" actually means that all submissions happen from a single thread that happens to be separate from the application's threads. If we only supported "multi-threaded submission", the fence handling could be simplified by adding the fences in that thread where everything is serialized.) Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add slab buffer listNicolai Hähnle2016-09-275-12/+107
| | | | | | | Introducing radeon_bo::hash will reduce collisions between "real" buffers and buffers from slabs. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: separate adding a buffer from updating its reloc dataNicolai Hähnle2016-09-271-35/+17
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add slab entry structures to radeon_boNicolai Hähnle2016-09-272-39/+78
| | | | | | Already adjust the map/unmap logic accordingly. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: enable buffer allocation from slabsNicolai Hähnle2016-09-274-0/+201
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add fence and buffer list logic for slab allocated buffersNicolai Hähnle2016-09-272-45/+149
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add slab entry structures to amdgpu_winsys_boNicolai Hähnle2016-09-273-36/+74
| | | | | | Already adjust amdgpu_bo_map/unmap accordingly. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: do not synchronize unsynchronized buffersNicolai Hähnle2016-09-273-45/+118
| | | | | | | | | | | | | | | | | | | | When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now no longer add a dependency on the buffer's fence(s). However, we still need to add a fence to the buffer during flush, so that cache reclaim works correctly (and in the hypothetical case that the buffer is later added to a CS _with_ the SYNCHRONIZED flag). It is now possible that the submissions refererring to a buffer are no longer linearly ordered, and so we may have to keep multiple fences around. We keep the fences in a FIFO. It should usually stay quite short (# of contexts * 2, for gfx + dma rings). While we're at it, extract amdgpu_add_fence_dependency for a single buffer, which will make adding the distinction between real buffer and slab cases easier. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add RADEON_FLAG_HANDLENicolai Hähnle2016-09-273-1/+7
| | | | | | | | | | | | | | | | When passed to winsys->buffer_create, this flag will indicate that we require a buffer that maps 1:1 with a kernel buffer handle. This is currently set for all textures, since textures can potentially be exported to other processes. This is not a huge loss, since the main purpose of this patch series is to deal with applications that allocate many small buffers. A hypothetical application with tons of tiny textures might still benefit from not setting this flag, but that's not a use case I'm worried about just now. Reviewed-by: Marek Olšák <[email protected]>
* i915g: add dma-buf support to i915_drm_buffer_get_handleNicholas Bishop2016-09-271-0/+6
| | | | | | | | | | | | | | | | The implementation of i915_drm_buffer_get_handle now handles DRM_API_HANDLE_TYPE_FD in the same way that intel_winsys_import_handle does, by calling drm_intel_bo_gem_create_from_prime. Tested by successfully running Chrome's ozone_demo [1] with the ozone-gbm backend on an Intel Pineview M machine. Without this change it fails while trying to create a DMA-BUF. [1] https://chromium.googlesource.com/chromium/src.git/+/master/ui/ozone/demo/ozone_demo.cc Signed-off-by: Nicholas Bishop <[email protected]> [Emil Velikov: Fix coding style] Signed-off-by: Emil Velikov <[email protected]>
* gallium: fix return value checkMartina Kollarova2016-09-141-6/+6
| | | | | | | | | A possible error (-1) was being lost because it was first converted to an unsigned int and only then checked. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Martina Kollarova <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* winsys/amdgpu: don't assume GTT if the VRAM flag isn't setMarek Olšák2016-09-131-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* android: add support for libmesa_amdgpu_addrlibMauro Rossi2016-09-131-4/+5
| | | | | | | | | | | Android porting of the following commits: f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place." 69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code" This patch fixes android building errors Reviewed-by: Dave Airlie <[email protected]>
* winsys/radeon: rename nrelocs, crelocs to max_relocs, num_relocsNicolai Hähnle2016-09-122-27/+27
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: don't pre-allocate the relocations arrayNicolai Hähnle2016-09-121-14/+1
| | | | | | It's really not necessary. Switch to an exponential resizing strategy. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: remove unused radeon_cs_context::priority_usageNicolai Hähnle2016-09-121-1/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: remove amdgpu_cs_lookup_bufferNicolai Hähnle2016-09-121-9/+0
| | | | | | | The radeonsi driver doesn't and shouldn't care about the buffer index. Only the virtual addresses matter. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: remove unused field domains from amdgpu_cs_bufferNicolai Hähnle2016-09-122-37/+17
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: remove initial buffer list allocationNicolai Hähnle2016-09-121-20/+0
| | | | | | It's really not necessary. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: extract adding a new buffer list entry into its own functionNicolai Hähnle2016-09-121-43/+70
| | | | | | | While at it, try to be a little more robust in the face of memory allocation failure. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: use only one fence per BONicolai Hähnle2016-09-123-68/+56
| | | | | | | | | | | The fence that is added to the BO during flush is guaranteed to be signaled after all the fences that were in the fences array of the BO before the flush, because those fences are added as dependencies for the submission (and all this happens atomically under the bo_fence_lock). Therefore, keeping only the last fence around is sufficient. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add do_winsys_deinit functionNicolai Hähnle2016-09-121-2/+7
| | | | | | | The idea is to have matching init/deinit functions so that deinit can be re-used for cleanup in the error path of amdgpu_winsys_create. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: clean up error paths in amdgpu_winsys_createNicolai Hähnle2016-09-121-7/+5
| | | | | | | No need to call pb_cache_deinit, because the cache hasn't been initialized at that point. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon/winsyses: remove #includes of pb_bufmgr.hNicolai Hähnle2016-09-123-3/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
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