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* gallium/radeon: pass create_screen flags to r600_common_screen_initMarek Olšák2017-06-234-8/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* svga: fix pre-mature flushing of the command bufferCharmaine Lee2017-06-222-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When surface_invalidate is called to invalidate a newly created surface in svga_validate_surface_view(), it is possible that the command buffer is already full, and in this case, currently, the associated wddm winsys function will flush the command buffer and resend the invalidate surface command. However, this can pre-maturely flush the command buffer if there is still pending image updates to be patched. To fix the problem, this patch will add a return status to the surface_invalidate interface and if it returns FALSE, the caller will call svga_context_flush() to do the proper context flush. Note, we don't call svga_context_flush() if surface_invalidate() fails when flushing the screen surface cache though, because it is already in the process of context flush, all the image updates are already patched, calling svga_context_flush() can trigger a deadlock. So in this case, we call the winsys context flush interface directly to flush the command buffer. Fixes driver errors and graphics corruption running Tropics. VMware bug 1891975. Also tested with MTT glretrace, piglit and various OpenGL apps such as Heaven, CinebenchR15, NobelClinicianViewer, Lightsmark, GoogleEarth. cc: [email protected] Reviewed-by: Brian Paul <[email protected]>
* winsys/amdgpu: fix a deadlock when waiting for submission_in_progressMarek Olšák2017-06-202-16/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First this happens: 1) amdgpu_cs_flush (lock bo_fence_lock) -> amdgpu_add_fence_dependency -> os_wait_until_zero (wait for submission_in_progress) - WAITING 2) amdgpu_bo_create -> pb_cache_reclaim_buffer (lock pb_cache::mutex) -> pb_cache_is_buffer_compat -> amdgpu_bo_wait (lock bo_fence_lock) - WAITING So both bo_fence_lock and pb_cache::mutex are held. amdgpu_bo_create can't continue. amdgpu_cs_flush is waiting for the CS ioctl to finish the job, but the CS ioctl is trying to release a buffer: 3) amdgpu_cs_submit_ib (CS thread - job entrypoint) -> amdgpu_cs_context_cleanup -> pb_reference -> pb_destroy -> amdgpu_bo_destroy_or_cache -> pb_cache_add_buffer (lock pb_cache::mutex) - DEADLOCK The simple solution is not to wait for submission_in_progress, which we need in order to create the list of dependencies for the CS ioctl. Instead of building the list of dependencies as a direct input to the CS ioctl, build the list of dependencies as a list of fences, and make the final list of dependencies in the CS thread itself. Therefore, amdgpu_cs_flush doesn't have to wait and can continue. Then, amdgpu_bo_create can continue and return. And then amdgpu_cs_submit_ib can continue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101294 Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: Add renderonly-based support for pl111+vc4.Eric Anholt2017-06-157-2/+169
| | | | | | | | | | | | | | | | | | | This follows the model of imx (display) and etnaviv (render): pl111 is a display-only device, so when asked to do GL for it, we see if we have a vc4 renderer, make the vc4 screen, and have vc4 call back to pl111 to do scanout allocations. The difference from etnaviv is that we share the same BO between vc4 and pl111, rather than having a vc4 bo and a pl11 bo and copies between the two. The only mismatch between their requirements is that vc4 requires 4-pixel (at 32bpp) stride alignment, while pl111 requires that stride match width. The kernel will reject any modesets to an incorrect stride, so the 3D driver doesn't need to worry about that. v2: Rebase on Android rework, drop unused include. v3: Fix another Android bug, from Rob Herring's build-testing. Reviewed-by: Christian Gmeiner <[email protected]>
* radeon/winsys: Limit max allocation size to 70% of VRAMAaron Watry2017-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CL CTS queries the max allocation size, and then attempts to allocate buffers of that size. If not enough contiguous RAM/VRAM is available, this causes errors in the radeon kernel module due to inability to allocate the required memory. It's a bit of a hack, but experimentally on my system, I can use ~3/4 of the card's VRAM for a single global/constant buffer allocation given current GUI/compositor use. For a 1GB Pitcairn (HD7850) this gets me from the reported clinfo values of: Global memory size 2143076352 (1.996GiB) Max memory allocation 1500153446 (1.397GiB) Max constant buffer size 1500153446 (1.397GiB) To: Global memory size 2143076352 (1.996GiB) Max memory allocation 751619276 (716MiB) Max constant buffer size 751619276 (716MiB) Fixes: OpenCL CTS test/conformance/api/min_max_mem_alloc_size, OpenCL CTS test/conformance/api/min_max_constant_buffer_size Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Use libdrm to get chipset nameSamuel Li2017-06-071-0/+8
| | | | | | | | v2: Add a func pointer to radeon_winsys to support radeon later. Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* util/u_queue: add an option to set the minimum thread priorityMarek Olšák2017-06-072-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add vcn dec cs supportLeo Liu2017-05-251-1/+10
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: rename has_uvd info to has_hw_decodeLeo Liu2017-05-251-2/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* winsys/amdgpu: align VA allocations to fragment size v2Christian König2017-05-241-0/+2
| | | | | | | | | | BOs larger than the minimum fragment size should have their VA alignet to at least the fragment size for optimal performance. v2: drop unused leftover from initial implementation Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: pipe AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS into gallium HUDMarek Olšák2017-05-232-0/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* virgl: fix virgl_bo_transfer_{put, get} box struct copyRob Herring2017-05-191-2/+12
| | | | | | | | | | | | | Commit 3dfe61ed6ec6 ("gallium: decrease the size of pipe_box - 24 -> 16 bytes") changed the size of pipe_box, but the virgl code was relying on pipe_box and drm_virtgpu_3d_box structs having the same size/layout doing a struct copy. Copy the fields one by one instead. Cc: Marek Olšák <[email protected]> Cc: Dave Airlie <[email protected]> Fixes: 3dfe61ed6ec ("gallium: decrease the size of pipe_box - 24 -> 16 bytes") Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add radeon_info::num_{sdma,compute}_ringsNicolai Hähnle2017-05-181-2/+2
| | | | | | Vulkan needs them. Reviewed-by: Marek Olšák <[email protected]>
* ac_surface: use radeon_info from ac_gpu_infoNicolai Hähnle2017-05-182-6/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move radeon_info initialization to amd/commonNicolai Hähnle2017-05-182-238/+4
| | | | | | v2: update Android.common.mk (Emil) Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move some aspects of sanity checking to ac_surfaceNicolai Hähnle2017-05-181-16/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add ac_compute_surface to automatically switch gfx6 vs. gfx9Nicolai Hähnle2017-05-181-4/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move the bulk of gfx9_surface_init to ac_surfaceNicolai Hähnle2017-05-181-415/+10
| | | | | | We can now merge the two *_surface_init functions. Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move the bulk of gfx6_surface_init to ac_surfaceNicolai Hähnle2017-05-181-411/+16
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: move amdgpu_addr_create to ac_surfaceNicolai Hähnle2017-05-183-165/+1
| | | | | | | | v2: - update Android.common.mk (Emil) - rebase on top of Raven support Reviewed-by: Marek Olšák <[email protected]> (v1)
* radeonsi/gfx9: add support for RavenMarek Olšák2017-05-151-0/+4
| | | | | | Cc: 17.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* Android: rework LLVM build supportRob Herring2017-05-111-0/+2
| | | | | | | | | | | | | Currently, building with "mmma external/mesa3d" which builds all targets and dependencies is broken for targets that require LLVM. This is due to the build settings depending on MESA_ENABLE_LLVM. Instead of using a conditional in the global Android.common.mk, make all the components that need LLVM explicitly include the necessary build settings. GALLIVM_CPP_SOURCES doesn't exist anymore, so remove that as well. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* Android: push driver build details to driver makefilesRob Herring2017-05-112-0/+9
| | | | | | | | | | | | | src/gallium/targets/dri/Android.mk contains lots of conditional for individual drivers. Let's move these details into the individual driver makefiles. In the process, align the make driver conditionals with automake (i.e. HAVE_GALLIUM_*). Signed-off-by: Rob Herring <[email protected]> [Emil Velikov: add the radeon winsys for radeonsi] Signed-off-by: Emil Velikov <[email protected]>
* Android: amd: use exported include dirs instead of explicit includesRob Herring2017-05-111-6/+1
| | | | | | | | | Add exported include paths rather than explicitly adding the includes in each user of the common AMD libs. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/amdgpu: fix Polaris12 (RX 550) breakageMarek Olšák2017-05-051-0/+1
| | | | | | | reported by Greg White. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100892 Cc: 17.1 <[email protected]>
* winsys/svga: fix error path when kernel is not able to create surfaceDeepak Rawat2017-04-261-15/+18
| | | | | | | | | | | If for some reason kernel is not able to create surface, when no buffer was provided the function vmw_svga_winsys_surface_create should return NULL. This patch fixes the issue where the code was not following the clean up path in case of error, which used to cause SIGSEGV. Reviewed-by: Sinclair Yeh <[email protected]>
* winsys/sw/dri: don't use GNU void pointer arithmeticEmil Velikov2017-04-191-1/+1
| | | | | | | | | | | | | | | Resolves build issues like the following: src/gallium/winsys/sw/dri/dri_sw_winsys.c:203:31: error: pointer of type ‘void *’ used in arithmetic [-Werror=pointer-arith] data = dri_sw_dt->data + (dri_sw_dt->stride * box->y) + box->x * blsize; ^ src/gallium/winsys/sw/dri/dri_sw_winsys.c:203:62: error: pointer of type ‘void *’ used in arithmetic [-Werror=pointer-arith] data = dri_sw_dt->data + (dri_sw_dt->stride * box->y) + box->x * blsize; ^ Cc: <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: init buffer_indices_hashlist with memset()Samuel Pitoiset2017-04-171-8/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: simplify amdgpu_cs_add_buffer() a bitSamuel Pitoiset2017-04-171-4/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* svga: remove unused vmw_dri1_intersect_src_bbox()Samuel Pitoiset2017-04-131-32/+0
| | | | | | | | | | | | Fixes the following Clang warning. vmw_screen_dri.c:130:1: warning: unused function 'vmw_dri1_intersect_src_bbox' [-Wunused-function] vmw_dri1_intersect_src_bbox(struct drm_clip_rect *dst, ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/radeon: add HUD queries for GPU temperature and clocksSamuel Pitoiset2017-04-101-1/+6
| | | | | | | | | | | | | | | Only the Radeon kernel driver exposed the GPU temperature and the shader/memory clocks, this implements the same functionality for the AMDGPU kernel driver. These queries will return 0 if the DRM version is less than 3.10, I don't explicitely check the version here because the query codepath is already a bit messy. v2: - rebase on top of master Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* svga: add context pointer to the invalidate surface interfaceCharmaine Lee2017-04-074-16/+19
| | | | | | | | | | | | | | With this patch, we will specify the current context when we invalidate the surface before the surface is put back to the recycled surface pool. This allows the winsys layer to use the specified context to do the invalidation rather than using the last context that referenced the surface. This prevents race condition if the last referenced context is now made current in another thread. Tested with MTT glretrace, NobelClinicianViewer. Reviewed-by: Sinclair Yeh <[email protected]>
* winsys/svga: use c11 thread types/functionsBrian Paul2017-04-073-13/+13
| | | | | | Gallium no longer has wrappers for mutexes and condition variables. Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga: Resolve command submission buffer contention v3Thomas Hellstrom2017-04-073-2/+38
| | | | | | | | | | | | | | | | | | | | | If two contexts wanted to access the same buffer at the same time, it would end up on two validation lists simultaneously, which might cause a PIPE_ERROR_RETRY when trying to validate it from one context while the other context already had it validated but not yet fenced. In that situation we could spin until the error goes away, or apply various more or less expensive locking schemes to save cpu. Here we use a scheme that briefly locks after fencing but avoids locking on validation in the non-contended case. v2: Make sure we broadcast not only on releasing buffers after fencing, but also after releasing buffers in the pb_validate_validate error path. v3: Don't broadcast on PIPE_ERROR_RETRY because that would increase the chance of starvation. Signed-off-by: Thomas Hellstrom <[email protected]>
* winsys/amdgpu: sparse buffer debugging helpersNicolai Hähnle2017-04-051-0/+61
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: take fences when freeing a backing bufferNicolai Hähnle2017-04-051-3/+11
| | | | | | | | | | | We never add fences to backing buffers during submit. When we free a backing buffer, it must inherit the sparse buffer's fences, so that it doesn't get re-used prematurely via the cache. v2: - remove pipe_mutex_* Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add sparse buffers to CSNicolai Hähnle2017-04-052-16/+140
| | | | | | | | | | ... and implement the corresponding fence handling. v2: - add missing bit in amdgpu_bo_is_referenced_by_cs_with_usage - remove pipe_mutex_* Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: sparse buffer creation / destruction / commitmentNicolai Hähnle2017-04-051-1/+400
| | | | | | | | | | | | | | This is the bulk of the buffer allocation logic. It is fairly simple and stupid. We'll probably want to use e.g. interval trees at some point to keep track of commitments, but Mesa doesn't have an implementation of those yet. v2: - remove pipe_mutex_* - fix total_backing_pages accounting - simplify by using the new VA_OP_CLEAR/REPLACE kernel interface Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add sparse buffer data structuresNicolai Hähnle2017-04-052-1/+46
| | | | | | | | v2: - remove pipe_mutex_* - use a simple page commitment array Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: extend amdgpu_add_fence to allow adding multiple fencesNicolai Hähnle2017-04-052-11/+27
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: build handles and flags list late on submit threadNicolai Hähnle2017-04-052-17/+28
| | | | | | | | | | | This probably has only minor performance effects, but it simplifies some subsequent code slightly. Ideally, it could also be used to simplify the handling of slab buffers in the same way, but unfortunately that's not possible as long as we need indices for relocations. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: share common code in amdgpu_add_fence_dependenciesNicolai Hähnle2017-04-051-21/+17
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: extract amdgpu_do_add_real_bufferNicolai Hähnle2017-04-051-8/+18
| | | | | | We will use it for delayed adding of sparse buffers' backing buffers. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: sparse buffers will not be supportedNicolai Hähnle2017-04-051-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: fix and enable single-sample CMASK fast clearMarek Olšák2017-03-311-0/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix and enable MSAA compressionMarek Olšák2017-03-311-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix linear mipmap CPU accessMarek Olšák2017-03-311-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: remove AMDGPU_INFO_NUM_EVICTIONSSamuel Pitoiset2017-03-301-4/+0
| | | | | | | | This is now exposed with libdrm_amdgpu 2.4.76. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/surface: add height pitch for gfx9Leo Liu2017-03-301-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]>
* winsys/amdgpu: set/get BO tiling flags for GFX9Marek Olšák2017-03-301-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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