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* svga: Add an environment variable to force coherent surface memoryThomas Hellstrom2019-05-174-3/+18
| | | | | | | | | | The vmwgfx driver supports emulated coherent surface memory as of version 2.16. Add en environtment variable to enable this functionality for texture- and buffer maps: SVGA_FORCE_COHERENT. This environment variable should be used for testing only. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flagsThomas Hellstrom2019-05-171-16/+7
| | | | | | | | | | | In order to be able to add access modes to a pb_validate_entry, update the pb_validate_add_buffer function to take a pointer hash table and also to return whether the buffer was already on the validate list. Update the svga winsys accordingly. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga: Fix RELOC_INTERNAL mob GPU accessThomas Hellstrom2019-05-171-1/+9
| | | | | | | | | | | | | | | SVGA_RELOC_INTERNAL indicates a transfer between surface and backing mob. This means that if the GPU for example reads from the surface it writes to the backing mob. But since the buffer mapping code allows for simultaneous gpu- and cpu read access, a read from the surface to the mob will not synchronize a subsequent map to the readback. Fix this by inverting the mob access mode in a surface relocation with SVGA_RELOC_INTERNAL set. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: Remove the surface_invalidate winsys functionThomas Hellstrom2019-05-173-18/+0
| | | | | | | | | | | Instead unconditionally call SVGA3D_InvalidateGBSurface() since it's needed also for Linux for dirty buffers and operation without SurfaceDMA. For non-guest-backed operation, remove the surface cache surface invalidation altogether. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2019-05-162-8/+0
| | | | This allows a nice cleanup, because the winsys always handles it.
* winsys/radeon: implement ctx_query_reset_status by copying radeonsiMarek Olšák2019-05-164-6/+43
| | | | | To make it behave like amdgpu. I'm just trying to move this out of radeonsi. The radeonsi code will be removed in the next commit.
* winsys/amdgpu: report a CS rejection as a reset only if there's no GPU resetMarek Olšák2019-05-161-6/+5
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* winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_spaceMarek Olšák2019-05-162-8/+15
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add a parallel compute IB coupled with a gfx IBMarek Olšák2019-05-163-5/+160
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: always set NO_CPU_ACCESS and NO_SUBALLOC on GDS resourcesMarek Olšák2019-05-161-2/+5
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* ac: rename SI-CIK-VI to GFX6-GFX7-GFX8Marek Olšák2019-05-155-24/+24
| | | | | | | | | | | | Acked-by: Dave Airlie <[email protected]> We already use GFX9 and I don't want us to have confusing naming in the driver. GFXn naming is better from the driver perspective, because it's the real version of the gfx portion of the hw. Also, CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI. It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have nothing to do with GFXn and they have their own version numbers.
* v3d: Use driconf to expose non-MSAA texture limits for Xorg.Eric Anholt2019-05-136-15/+25
| | | | | | The V3D 4.2 HW has a limit to MSAA texture sizes of 4096. With non-MSAA, we can go up to 7680 (actually probably 8138, but that hasn't been validated by the HW team). Exposing 7680 in X11 will allow dual 4k displays.
* winsys/amdgpu: add VCN JPEG to no user fence groupLeo Liu2019-05-101-1/+2
| | | | | | | | | | There is no user fence for JPEG, the bug triggering kernel WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT) Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: [email protected]
* virgl: export resource_is_busy from winsysChia-I Wu2019-05-062-11/+14
| | | | | Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* svga: move host logging to winsysCharmaine Lee2019-05-025-0/+495
| | | | | | | | | This patch adds a host_log interface to svga_winsys and moves the host logging code to the winsys layer. Cc: [email protected] Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Neha Bhende <[email protected]>
* winsys/svga: Don't abort on EBUSY errors from execbufferThomas Hellstrom2019-05-021-1/+3
| | | | | | | | | | This error code typically indicated that a buffer object that was referenced by the command stream was being used for CPU access by another client. The correct action here is to retry after a while. Use usleep() until we have proper kernel support for this wait. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* winsys/svga: Update the drm interface fileThomas Hellstrom2019-05-022-174/+188
| | | | | | | | The file vmwgfx_drm.h was a bit outdated. Update to a recent version, including defines supporting coherent memory. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* winsys/svga: Enable the transfer_from_buffer GPU command for vgpu10Thomas Hellstrom2019-05-021-0/+1
| | | | | | | | | | We didn't have the path using this command enabled as typically we take an alternate path using DMA uploads. Emable it so that we can exercise that code-path by turning off the DMA path. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* winsys/svga: Add an environment variable to force host-backed operationThomas Hellstrom2019-05-021-6/+11
| | | | | | | | | | | | The vmwgfx kernel module has a compatibility mode for user-space that is not guest-backed resource aware. Add an environment variable to facilitate testing of this mode on guest-backed aware kernels: if the environment variable SVGA_FORCE_HOST_BACKED is defined, the driver will use host-backed operation. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Deepak Rawat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* winsys/svga/drm: Include sys/types.hKhem Raj2019-04-301-0/+1
| | | | | | | | | | vmw_screen.h uses dev_t which is defines in sys/types.h this header is required to be included for getting dev_t definition. This issue happens on musl C library, it is hidden on glibc since sys/types.h is included through another system headers Reviewed-by: Eric Engestrom <[email protected]>
* vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.Eric Anholt2019-04-262-3/+35
| | | | | | | I have a platform with vc4 display but V3D 4.x. We can fall back on kmsro's probing to bring up the v3d gallium driver. Acked-by: Rob Clark <[email protected]>
* kmsro: Add support for V3D.Eric Anholt2019-04-262-0/+16
| | | | | | | | | Like vc4, we expect to have SOCs with various displays that have a single V3D instance for rendering. v2: Add v3d to the list of drivers that make enabling kmsro valid. Acked-by: Rob Clark <[email protected]>
* virgl/drm: insert correct handles into the table. (v3)Dave Airlie2019-04-251-1/+4
| | | | | | | | | | This inserts a handle for the flink name and a handle the correct gem handle for the bo. v2: fix handles/names confusion (Lepton Wu) v3: set flink name correctly (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: handle flink name better.Dave Airlie2019-04-252-20/+11
| | | | | | This realigns this code with code from radeon. Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2019-04-252-15/+13
| | | | | | | | This cleans up and realigns this code with what is in radeon v2: fix names->handles (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* winsys/amdgpu: clean up and remove nonsensical assertionMarek Olšák2019-04-231-2/+1
| | | | | | | | The assertion considers max_dw from the current IB in the chain, but big_ib_buffer is a buffer for the next IB, which can be smaller. Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: enable chaining for compute IBsMarek Olšák2019-04-231-6/+6
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE lastMarek Olšák2019-04-231-19/+17
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-231-1/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-231-7/+0
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* iris: Add mechanism for iris-specific driconf optionsKenneth Graunke2019-04-222-3/+5
| | | | | | Based on Nicolai's 0f8c5de8690e7c87aa2e24383065efaca7e6fe78. Reviewed-by: Dylan Baker <[email protected]>
* lima: add Android buildIcenowy Zheng2019-04-211-0/+32
| | | | | | | | | Currently only meson build supported is added for lima driver. Add Android build support for lima. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Qiang Yu <[email protected]>
* virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh2019-04-183-3/+12
| | | | | | | | This more accurately reflects what the drm winsys does. Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: wait after issuing a transfer getGurchetan Singh2019-04-181-2/+3
| | | | | | | | | | | | Otherwise, there's artifacts when running Unigine Valley with protocol version 2. We can get away with not waiting for most buffers, but let's be conservative. Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh2019-04-181-4/+35
| | | | | | | | We need to copy the shared memory region to the display target. Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: receive and handle shared memory fdGurchetan Singh2019-04-182-7/+55
| | | | | | | | | | | | | | | | The only tricky part is with protocol 0 we can either have a display target or resource backing store. With protocol 2 we can have both. Make the map/unmap functions only deal with the resource backing store. v2: Handle MSAA texture case. v3: spelling v4: Fix dangling else (@prak) v5: mmap --> os_mmap (@prak) + added comments (@gerddie) Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: plumb support for shared memoryGurchetan Singh2019-04-183-6/+10
| | | | | | Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: add utilities for receiving fdsGurchetan Singh2019-04-181-0/+43
| | | | | | | | v2: recieve --> receive (airlied@) Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* virgl/vtest: execute a transfer_get when flushing the front bufferGurchetan Singh2019-04-181-22/+21
| | | | | | | | | | | | This just moves everything to a helper function -- "flush_front_buffer" will be used later. virgl_vtest_resource_map / virgl_vtest_resource_unmap already take care to map the display target. Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* winsys/amdgpu: don't set GTT with GDS & OA placements on APUsMarek Olšák2019-04-161-9/+11
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* virgl: fix fence fd version checkChia-I Wu2019-04-151-2/+2
| | | | | | | Fixes: d1a1c21e762 ("virgl: native fence fd support") Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: introduce virgl_drm_fenceChia-I Wu2019-04-152-45/+115
| | | | | | | | | virgl_drm_fence can wrap either a fence fd or a virgl_hw_res. Because a fence fd is cheaper than a virgl_hw_res, we use it whenever it is available. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: hide fence internals from the driverChia-I Wu2019-04-152-28/+42
| | | | | | | | | | | | | | Fence fds are cheaper than resources. We want to let winsys make the decision and use fence fds whenever they are supported. This commit prepares the work. For the moment, we create a resource _and_ a fence fd when supports_fences is true. This will be fixed such that we create a resource _or_ a fence fd. (And because of a version check bug that we will fix later, supports_fences is actually never true). Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: handle fence_server_sync in winsysChia-I Wu2019-04-153-12/+25
| | | | | | | | It does not need help from the driver. This also fixes one issue where the fence is ignored when the transfer queue is full. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* Delete autotoolsDylan Baker2019-04-1519-606/+0
| | | | | | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Matt Turner <[email protected]>
* ac: Move has_local_buffers disable to radeonsi.Bas Nieuwenhuizen2019-04-151-0/+4
| | | | | | | | | | | | | | In radv we had a separate flag to actually use it + an env option to experimentally use it. The common code setting has_local_buffers to false of course broke that experimental option. Also the "enable on APU" did not make sense for RADV as it is still disabled by default. Fixes: b21a4efb553 "radv/winsys: allow local BOs on APUs" Reviewed-by: Samuel Pitoiset <[email protected]>
* kmsro: Add lima renderonly supportRob Herring2019-04-112-0/+14
| | | | | | | | | Enable using lima for KMS renderonly. This still needs KMS driver name mapping to kmsro to be used automatically. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
* gallium: add lima driverQiang Yu2019-04-113-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: - use renamed util_dynarray_grow_cap - use DEBUG_GET_ONCE_FLAGS_OPTION for debug flags - remove DRM_FORMAT_MOD_ARM_AGTB_MODE0 usage - compute min/max index in driver v3: - fix plbu framebuffer state calculation - fix color_16pc assemble - use nir_lower_all_source_mods for lowering neg/abs/sat - use float arrary for static GPU data - add disassemble comment for static shader code - use drm_find_modifier v4: - use lima_nir_lower_uniform_to_scalar v5: - remove nir_opt_global_to_local when rebase Cc: Rob Clark <[email protected]> Cc: Alyssa Rosenzweig <[email protected]> Acked-by: Eric Anholt <[email protected]> Signed-off-by: Andreas Baierl <[email protected]> Signed-off-by: Arno Messiaen <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Signed-off-by: Erico Nunes <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Koen Kooi <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: marmeladema <[email protected]> Signed-off-by: Paweł Chmiel <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Rohan Garg <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
* radeonsi: add support for displayable DCC for 1 RB chipsMarek Olšák2019-04-041-0/+8
| | | | This is the simpler codepath - just disable RB and pipe alignment for DCC.
* panfrost: Remove support for legacy kernelsAlyssa Rosenzweig2019-04-033-14/+5
| | | | | | | | | | | | | | Previously, there was minimal support for interoperating with legacy kernels (reusing kernel modules originally designed for proprietary legacy userspaces, rather than for upstream-friendly free software stacks). Now that the Panfrost kernel is stabilising, this commit drops the legacy code path. Panfrost users need to use a modern, mainline kernel supporting the Panfrost kernel driver from this commit forward. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
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