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* nvc0: add initial support for nve4+ (Kepler) chipsetsChristoph Bumiller2012-04-151-0/+1
| | | | | | | | | Most things that work on Fermi should work on Kepler too. There are a few performance optimizations left to do, like better placement of texture barriers and adding scheduling data to the shader instructions (without them, a thread group will be masked for 32 cycles after each single instruction issue).
* nv30: import new driver for GeForce FX/6/7 chipsets, and Quadro variantsBen Skeggs2012-04-141-2/+0
| | | | | | | | | | | | | | | | | | The primary motivation for this rewrite was to have a maintainable driver going forward, as nvfx was quite horrible in a lot of ways. The driver is heavily based on the design of the nv50/nvc0 3d drivers we already have, and uses the same common buffer/fence code. It also passes a HEAP more piglit tests than nvfx did, supports a couple more features, and a few more to come still probably. The CPU footprint of this driver is far far less than nvfx, and translates into far greater framerates in a lot of applications (unless you're using a CPU that's way way newer than the GPUs of these generations....) Basically, we once again have a maintained driver for these chipsets \o/ Feel free to report bugs now!
* nouveau: switch to libdrm_nouveau-2.0Christoph Bumiller2012-04-141-5/+1
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* nvfx: completely remove this driver (GeForce FX/6/7)Ben Skeggs2012-04-141-1/+3
| | | | | | | | | | This driver hasn't been maintained properly for a very long time, and for many very good reasons. It's horrible. A new driver supporting these chipsets will appear with the commits that port vieux/nv50/nvc0 to libdrm_nouveau-2.0. Signed-off-by: Ben Skeggs <[email protected]>
* radeonsi: initial WIP SI codeTom Stellard2012-04-132-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <[email protected]> Michel Dänzer <[email protected]> Alex Deucher <[email protected]> Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <[email protected]> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <[email protected]> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <[email protected]> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <[email protected]> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <[email protected]> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
* st/egl: Update to the new wl_shm_pool interfaceBenjamin Franzke2012-04-032-0/+2
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* r600g: optimize r600_resource_vaMarek Olšák2012-04-012-5/+3
| | | | Avoid calling get_radeon_bo and inline it.
* vl: move winsys helper out of winsys directoryChristian König2012-03-285-651/+0
| | | | | | | | | They aren't winsys of their own, just help dealing with them. v2: add some more comments in vl_winsys.h Signed-off-by: Christian König <[email protected]>
* r600g: enable transform feedback on everything that isn't r700Marek Olšák2012-03-271-2/+1
| | | | Use R700_STREAMOUT=1 if you wanna hack transform feedback on r700.
* vl: handle DRI2GetBuffers reply with multiple buffersChristian König2012-03-091-10/+23
| | | | | | This fixes a crash in XBMC, but we still doesn't see a picture. Signed-off-by: Christian König <[email protected]>
* st/vdpau: implement support for high-precision output timingChristian König2012-03-053-31/+133
| | | | Signed-off-by: Christian König <[email protected]>
* winsys/radeon: cleanup includesMarek Olšák2012-03-051-3/+1
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* winsys/radeon: add usage parameter to cs_is_buffer_referencedMarek Olšák2012-03-052-3/+18
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: move dirty area handling into winsys abstractionChristian König2012-03-013-2/+48
| | | | | | Fixing uninitialized areas in SwapBuffers mode. Signed-off-by: Christian König <[email protected]>
* vl: hide X latency by using asynchronous requestsChristian König2012-03-011-11/+37
| | | | Signed-off-by: Christian König <[email protected]>
* vl: use SwapBuffers instead of CopyBuffersChristian König2012-03-011-40/+9
| | | | | | | | | This should speed things up a bit, but also shows some bugs with the kernel implementation. v2: require xcb-dri2 version 1.8 Signed-off-by: Christian König <[email protected]>
* vl: rewrite vl DRI backend using XCBChristian König2012-03-014-856/+145
| | | | | | v2: also set array_size of texture Signed-off-by: Christian König <[email protected]>
* vl: fix a douple free in xsp winsys backendChristian König2012-02-271-1/+1
| | | | | | | There are a couple of more bugs, but it is only useful for debugging anyway. Signed-off-by: Christian König <[email protected]>
* r600g: check for R600_STREAMOUT env var in winsysMarek Olšák2012-02-272-0/+5
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* vl: rework winsys interfaceChristian König2012-02-253-185/+54
| | | | | | Throw out all the old and now unneeded stuff. Signed-off-by: Christian König <[email protected]>
* vl: cleanup dri winsys abstractionChristian König2012-02-257-1575/+56
| | | | | | There was way to much dead code in it. Signed-off-by: Christian König <[email protected]>
* radeon/r600g: fix virtual address space allocationJerome Glisse2012-02-211-0/+3
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix tiling with cayman and virtual memoryJerome Glisse2012-02-141-10/+28
| | | | | | | | | The virtual address but follow the alignment requirement of the tiled surface. The bo from handle case is not properly fix. Need bigger change for a proper fix. Work around that by enforcing 1M alignment for those bo. Signed-off-by: Jerome Glisse <[email protected]>
* radeon: only init surface manage on r600Dave Airlie2012-02-071-4/+8
| | | | | | r300 fails to init the manager and then fails to init. Signed-off-by: Dave Airlie <[email protected]>
* scons: r300/r600 now depends on libdrm.José Fonseca2012-02-072-36/+1
| | | | As they now indirectly include on libdrm/radeon_surface.h.
* r600g: add support for common surface allocator for tiling v13Jerome Glisse2012-02-064-2/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]>
* r600g: remove unused flush codeMarek Olšák2012-01-312-13/+1
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* vl: fix some missing prototypes errorChristian König2012-01-311-27/+0
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45444 Signed-off-by: Christian König <[email protected]>
* r600g: add support for virtual address space on cayman v11Jerome Glisse2012-01-136-10/+273
| | | | | | | | | | | | | | | | | | | | | | | | | Virtual address space put the userspace in charge of their GPU address space. It's up to userspace to bind bo into the virtual address space. Command stream can them be executed using the IB_VM chunck. This patch add support for this configuration. It doesn't remove the 64K ib size limit thought this limit can be extanded up to 1M for IB_VM chunk. v2: fix rendering v3: fix rendering when using index buffer v4: make vm conditional on kernel support add basic va management v5: catch the case when we already have va for a bo v6: agd5f: update on top of ioctl changes v7: agd5f: further ioctl updates v8: indentation cleanup + fix non cayman v9: rebase against lastest mesa + improvement from Marek & Michel v10: fix cut/paste bug v11: don't rely on updated radeon_drm.h Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* svga: Drop execbuf throttlingJakob Bornecrantz2012-01-104-35/+1
| | | | | | | | This code isn't used anymore in preference for DRI2 client side swap buffers throttling or throttling done inside the xa or xorg driver. Signed-off-by: Jakob Bornecrantz <[email protected]> Reviewed-by Brian Paul <[email protected]>
* svga: Silence warningJakob Bornecrantz2012-01-101-0/+1
| | | | | Signed-off-by: Jakob Bornecrantz <[email protected]> Reviewed-by Brian Paul <[email protected]>
* radeon/winsys: fix get info ioctl error checkingJerome Glisse2012-01-091-3/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* winsys/radeon: move managing GEM domains back to driversMarek Olšák2011-12-244-56/+40
| | | | | | | | This partially reverts commit 363ff844753c46ac9c13866627e096b091ea81f8. It caused severe performance drops in Nexuiz. Reported by Phoronix. Tested by me on r300g and by IRC people on r600g.
* nouveau: get rid of winsys objectMarcin Slusarz2011-12-133-86/+2
| | | | Its only purpose was to destroy itself.
* winsys/radeon: add flush option not to rewrite tiling flags in registersMarek Olšák2011-12-133-4/+24
| | | | Not used yet.
* g3dvl/xlib: fix build by changing include orderTobias Droste2011-12-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | fixes the following build error since c83fb4d45f2a47042f395271efe6e5489b2c4aee: /usr/include/strings.h:46:13: error: expected declaration specifiers or ‘...’ before numeric constant /usr/include/strings.h:46:13: error: conflicting types for ‘memset’ In file included from ../../../../src/gallium/winsys/g3dvl/xlib/xsp_winsys.c:34:0: ../../../../src/gallium/auxiliary/util/u_inlines.h: In function ‘pipe_buffer_create’: ../../../../src/gallium/auxiliary/util/u_inlines.h:189:4: error: too many arguments to function ‘memset’ /usr/include/strings.h:46:13: note: declared here bzero is defined in X11 as: #define bzero(b,len) memset(b,0,len) including strings.h after the X11 header results in preprocessor replacing 'bzero' in strings.h and generating unbuildable code. Signed-off-by: Tobias Droste <[email protected]>
* gallium/radeon: fix indentationJerome Glisse2011-12-054-28/+28
| | | | | | Indentation cleanup, to keep consistency. Signed-off-by: Jerome Glisse <[email protected]>
* i965g: Delete this driver.Kai Wasserbäch2011-11-299-1286/+0
| | | | | | | Never completed, and no plans to do so. Signed-off-by: Kai Wasserbäch <[email protected]> Signed-off-by: José Fonseca <[email protected]>
* android: add support for ICSChia-I Wu2011-11-251-19/+28
| | | | | | | | With ICS (Android 4.0), several headers and structs are renamed. Define ANDROID_VERSION so that we can choose a different path depending on the platform version. I've tested only softpipe and llvmpipe. r600g is also reported to work.
* nvc0: add support for GF119 (NVD9)Ben Skeggs2011-11-171-0/+1
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* radeon: silence initializer warningsBrian Paul2011-11-102-11/+33
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* dri: drop DRI_VALIDATE macrosGeorge Sapountzis2011-11-041-24/+0
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* winsys/radeon: don't use the new GEM_WAIT ioctl for nowMarek Olšák2011-10-241-4/+6
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* winsys/radeon: restore the old r600g winsys memory characteristics.Mathias Fröhlich2011-10-241-0/+5
| | | | | | | | | Use VRAM for static and immutable buffers. This restores the recently removed r600g winsys behaviour for memory locations. This also improoves rendering times on the gpu for some OpenSceneGraph based test cases by about 15%. Signed-off-by: Marek Olšák <[email protected]>
* winsys/svga: Remove some unneeded debug codeThomas Hellstrom2011-10-191-16/+0
| | | | | | | | | | | This code isn't really relevant since the kernel takes care not to destroy busy GMR buffers. Also with the advent of fence objects, the code was incorrect since it didn't refcount fence handles. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* winsys/svga: Rework buffer allocation to make it more robust v2.Thomas Hellstrom2011-10-143-17/+57
| | | | | | | | | | | | | | | | Don't allow any "CPU" buffers to be allocated by the pb_fenced buffer manager, since we can't protect against failures during buffer validation. Also, add an extra slab buffer manager to allocate buffers from the kernel if there is a failure to allocate from our big buffer pool. The reason we use a slab manager for this, is to avoid allocating many very small buffers from the kernel. v2: Increased VMW_MAX_BUFFER_SIZE and fixed some comments. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* svga/winsys: Make sure a flush always inserts and returns a fence if requestedThomas Hellstrom2011-10-141-1/+1
| | | | | | | Needed for throttling. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrant <[email protected]>
* configure: replace pkg-config calls with $(PKG_CONFIG) in the makefiles.Stéphane Marchesin2011-10-046-10/+10
| | | | | | | Us poor souls who cross compile mesa want to be able to specify which pkg-config to pick, or at least just change one place. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* r600g: move all files from winsys/r600 into drivers/r600Marek Olšák2011-09-308-3294/+0
| | | | | | Be sure to reconfigure after this commit. Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: move GEM domains out of the drivers into winsysMarek Olšák2011-09-305-46/+60
| | | | | | | | | | | | | | | The drivers don't need to care about the domains. All they need to set are the bind and usage flags. This simplifies the winsys too. This also fixes on r600g: - fbo-depth-GL_DEPTH_COMPONENT32F-copypixels - fbo-depth-GL_DEPTH_COMPONENT16-copypixels - fbo-depth-GL_DEPTH_COMPONENT24-copypixels - fbo-depth-GL_DEPTH_COMPONENT32-copypixels - fbo-depth-GL_DEPTH24_STENCIL8-copypixels I can't explain it. Reviewed-by: Alex Deucher <[email protected]>
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