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* Revert "winsys/amdgpu: disable local BOs on Raven"Marek Olšák2017-09-121-2/+1
| | | | | | This reverts commit 1cda9a2fee05effd9c64bd773bc6005281593662. It works now.
* winsys/amdgpu: use the new raw CS APIMarek Olšák2017-09-112-77/+93
| | | | | | This also cleans things up. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement pipe_context::fence_server_syncMarek Olšák2017-09-111-0/+16
| | | | | | This will be more useful once we have sync_file support. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: factor out some fence dependency code into separate functionsMarek Olšák2017-09-111-21/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: rename fence_dependency functionsMarek Olšák2017-09-111-12/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: don't allow interprocess resource sharing for IBsMarek Olšák2017-09-111-1/+2
| | | | | | | Now we should get IB submissions with bo_list == NULL when DRI buffers aren't referenced. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add radeon_surf::has_stencil for convenienceMarek Olšák2017-09-071-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: disable local BOs on RavenMarek Olšák2017-09-071-1/+2
| | | | | | It hangs with a high degree of reproducibility. Acked-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2Christian König2017-08-313-5/+27
| | | | | | | | | | | When the kernel supports it set the local flag and stop adding those BOs to the BO list. Can probably be optimized much more. v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: set a per-buffer flag that disables inter-process sharing (v4)Marek Olšák2017-08-312-24/+33
| | | | | | | | | | | For lower overhead in the CS ioctl. Winsys allocators are not used with interprocess-sharable resources. v2: It shouldn't crash anymore, but the kernel will reject the new flag. v3 (christian): Rename the flag, avoid sending those buffers in the BO list. v4 (christian): Remove setting the kernel flag for now Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add BO to the global list only when RADEON_ALL_BOS is setSamuel Pitoiset2017-08-304-11/+17
| | | | | | | Only useful when that debug option is enabled. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove Constant Engine supportMarek Olšák2017-08-222-108/+2
| | | | | | | | We have come to the conclusion that it doesn't improve performance. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: print all members of radeon_info with R600_DEBUG=infoMarek Olšák2017-08-071-1/+1
| | | | | | | also set max_alignment on amdgpu. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: enable computation of tile swizzleMarek Olšák2017-08-042-1/+13
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: increment surf_index only when tile swizzle is allowedMarek Olšák2017-08-041-0/+1
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add pipe_screen_config to screen_create functionsNicolai Hähnle2017-08-024-8/+10
| | | | | | | This allows a more generic mechanism for passing user configurations into drivers by accessing the dri options directly. Reviewed-by: Marek Olšák <[email protected]>
* winsys/svga/drm: Enable import/export fence FDSinclair Yeh2017-07-173-19/+53
| | | | | | | | | Enable the capability if the DRM supports it. Hook up mechanism to send and receive fence FD from the DRM. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga/drm: Connect winsys-side fence_* functionsSinclair Yeh2017-07-174-10/+109
| | | | | | | | | Connect fence_get_fd, fence_create_fd, and fence_server_sync. Implement the required functions in vmw_fence module. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga/drm: Prepare to support fence fdSinclair Yeh2017-07-171-3/+8
| | | | | | | Make the fields and flags available. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* drivers/svga, winsys/svga/drm: Thread through timeout for fence_finishSinclair Yeh2017-07-173-2/+6
| | | | | | | | | | | | The timeout parameter is required to implement EGL_ANDROID_native_fence_sync. v2 * Replaced default timeout from 0 to PIPE_TIMEOUT_INFINITE * Add more documentation to the new timeout parameter Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* radeonsi: prevent a deadlock in util_queue_add_job with too many GL contextsMarek Olšák2017-07-171-1/+2
| | | | | | | | | | | | | | | | If the queue is full, util_queue_add_job will wait while bo_fence_lock is held. It pb_slab wants to reuse a buffer, it will lock the pb_slab mutex and try to check BO fence busyness, but it has to wait for bo_fence_lock to get released. Both bo_fence_lock and pb_slab mutex are locked now. When the CS thread unreferences and releases a suballocated buffer, it will try to lock the pb_slab mutex and has to wait. The CS thread can't finish its job in order to free a queue slot and unblock util_queue_add_job ==> deadlock. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: use "ull" number suffix to keep the QtCreator parser happyMarek Olšák2017-07-102-2/+2
| | | | | | | It can't parse "llu". Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* radv: add support for using addrlib max alignment.Dave Airlie2017-07-091-1/+1
| | | | | | | | Rather than using 64k, use what addrlib returns as the base alignment for vulkan allocations. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* android: build imx-drm winsysTomeu Vizoso2017-07-051-0/+40
| | | | | | | | Add Android.mk for winsys/imx/drm. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: add etnaviv driver build supportRob Herring2017-07-051-0/+33
| | | | | | | | Add etnaviv to Android makefiles. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOsMarek Olšák2017-07-042-3/+5
| | | | | | | | | | This decreases the number of BOs, but might also increase memory usage. It's better for small textures. The gameplay is on the far right: https://people.freedesktop.org/~mareko/suballoc.svg Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add radeon_winsys::buffer_is_suballocatedMarek Olšák2017-07-042-0/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up pb_cache bucket/usage determinationMarek Olšák2017-07-042-32/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: enable suballocations for VRAM with no CPU accessMarek Olšák2017-07-042-0/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up (domain, flags) <-> (slab heap) translationsMarek Olšák2017-07-044-74/+17
| | | | | | This is cleaner, and we are down to 4 slabs. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove RADEON_FLAG_CPU_ACCESSMarek Olšák2017-07-043-17/+3
| | | | | | https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disallow exports of sparse and suballocated BOsMarek Olšák2017-07-042-8/+6
| | | | | | I think it's unsafe, because the slabs can reuse exported storage. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOCMarek Olšák2017-07-043-6/+6
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a HUD query for getting an average GFX BO list sizeMarek Olšák2017-07-044-0/+7
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: only call pb_slabs_reclaim when slabs are actually usedNicolai Hähnle2017-07-031-1/+2
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100242 Fixes: fb827c055cb1 ("winsys/radeon: enable buffer allocation from slabs") Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i915: use different CFLAGS/LIBS variables than i965/anvLionel Landwerlin2017-06-271-1/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* gallium/radeon: pass create_screen flags to r600_common_screen_initMarek Olšák2017-06-234-8/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* svga: fix pre-mature flushing of the command bufferCharmaine Lee2017-06-222-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When surface_invalidate is called to invalidate a newly created surface in svga_validate_surface_view(), it is possible that the command buffer is already full, and in this case, currently, the associated wddm winsys function will flush the command buffer and resend the invalidate surface command. However, this can pre-maturely flush the command buffer if there is still pending image updates to be patched. To fix the problem, this patch will add a return status to the surface_invalidate interface and if it returns FALSE, the caller will call svga_context_flush() to do the proper context flush. Note, we don't call svga_context_flush() if surface_invalidate() fails when flushing the screen surface cache though, because it is already in the process of context flush, all the image updates are already patched, calling svga_context_flush() can trigger a deadlock. So in this case, we call the winsys context flush interface directly to flush the command buffer. Fixes driver errors and graphics corruption running Tropics. VMware bug 1891975. Also tested with MTT glretrace, piglit and various OpenGL apps such as Heaven, CinebenchR15, NobelClinicianViewer, Lightsmark, GoogleEarth. cc: [email protected] Reviewed-by: Brian Paul <[email protected]>
* winsys/amdgpu: fix a deadlock when waiting for submission_in_progressMarek Olšák2017-06-202-16/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First this happens: 1) amdgpu_cs_flush (lock bo_fence_lock) -> amdgpu_add_fence_dependency -> os_wait_until_zero (wait for submission_in_progress) - WAITING 2) amdgpu_bo_create -> pb_cache_reclaim_buffer (lock pb_cache::mutex) -> pb_cache_is_buffer_compat -> amdgpu_bo_wait (lock bo_fence_lock) - WAITING So both bo_fence_lock and pb_cache::mutex are held. amdgpu_bo_create can't continue. amdgpu_cs_flush is waiting for the CS ioctl to finish the job, but the CS ioctl is trying to release a buffer: 3) amdgpu_cs_submit_ib (CS thread - job entrypoint) -> amdgpu_cs_context_cleanup -> pb_reference -> pb_destroy -> amdgpu_bo_destroy_or_cache -> pb_cache_add_buffer (lock pb_cache::mutex) - DEADLOCK The simple solution is not to wait for submission_in_progress, which we need in order to create the list of dependencies for the CS ioctl. Instead of building the list of dependencies as a direct input to the CS ioctl, build the list of dependencies as a list of fences, and make the final list of dependencies in the CS thread itself. Therefore, amdgpu_cs_flush doesn't have to wait and can continue. Then, amdgpu_bo_create can continue and return. And then amdgpu_cs_submit_ib can continue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101294 Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: Add renderonly-based support for pl111+vc4.Eric Anholt2017-06-157-2/+169
| | | | | | | | | | | | | | | | | | | This follows the model of imx (display) and etnaviv (render): pl111 is a display-only device, so when asked to do GL for it, we see if we have a vc4 renderer, make the vc4 screen, and have vc4 call back to pl111 to do scanout allocations. The difference from etnaviv is that we share the same BO between vc4 and pl111, rather than having a vc4 bo and a pl11 bo and copies between the two. The only mismatch between their requirements is that vc4 requires 4-pixel (at 32bpp) stride alignment, while pl111 requires that stride match width. The kernel will reject any modesets to an incorrect stride, so the 3D driver doesn't need to worry about that. v2: Rebase on Android rework, drop unused include. v3: Fix another Android bug, from Rob Herring's build-testing. Reviewed-by: Christian Gmeiner <[email protected]>
* radeon/winsys: Limit max allocation size to 70% of VRAMAaron Watry2017-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CL CTS queries the max allocation size, and then attempts to allocate buffers of that size. If not enough contiguous RAM/VRAM is available, this causes errors in the radeon kernel module due to inability to allocate the required memory. It's a bit of a hack, but experimentally on my system, I can use ~3/4 of the card's VRAM for a single global/constant buffer allocation given current GUI/compositor use. For a 1GB Pitcairn (HD7850) this gets me from the reported clinfo values of: Global memory size 2143076352 (1.996GiB) Max memory allocation 1500153446 (1.397GiB) Max constant buffer size 1500153446 (1.397GiB) To: Global memory size 2143076352 (1.996GiB) Max memory allocation 751619276 (716MiB) Max constant buffer size 751619276 (716MiB) Fixes: OpenCL CTS test/conformance/api/min_max_mem_alloc_size, OpenCL CTS test/conformance/api/min_max_constant_buffer_size Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Use libdrm to get chipset nameSamuel Li2017-06-071-0/+8
| | | | | | | | v2: Add a func pointer to radeon_winsys to support radeon later. Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* util/u_queue: add an option to set the minimum thread priorityMarek Olšák2017-06-072-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add vcn dec cs supportLeo Liu2017-05-251-1/+10
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: rename has_uvd info to has_hw_decodeLeo Liu2017-05-251-2/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* winsys/amdgpu: align VA allocations to fragment size v2Christian König2017-05-241-0/+2
| | | | | | | | | | BOs larger than the minimum fragment size should have their VA alignet to at least the fragment size for optimal performance. v2: drop unused leftover from initial implementation Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: pipe AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS into gallium HUDMarek Olšák2017-05-232-0/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* virgl: fix virgl_bo_transfer_{put, get} box struct copyRob Herring2017-05-191-2/+12
| | | | | | | | | | | | | Commit 3dfe61ed6ec6 ("gallium: decrease the size of pipe_box - 24 -> 16 bytes") changed the size of pipe_box, but the virgl code was relying on pipe_box and drm_virtgpu_3d_box structs having the same size/layout doing a struct copy. Copy the fields one by one instead. Cc: Marek Olšák <[email protected]> Cc: Dave Airlie <[email protected]> Fixes: 3dfe61ed6ec ("gallium: decrease the size of pipe_box - 24 -> 16 bytes") Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add radeon_info::num_{sdma,compute}_ringsNicolai Hähnle2017-05-181-2/+2
| | | | | | Vulkan needs them. Reviewed-by: Marek Olšák <[email protected]>
* ac_surface: use radeon_info from ac_gpu_infoNicolai Hähnle2017-05-182-6/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
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