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* winsys/amdgpu: always allow GTT placements on APUsMarek Olšák2018-03-261-7/+5
| | | | Reviewed-by: Christian König <[email protected]>
* radeonsi: don't reallocate on DMABUF export if local BOs are disabledMarek Olšák2018-03-261-4/+3
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* gallium/winsys/kms: Add support for multi-planesLepton Wu2018-03-221-40/+112
| | | | | | | | | | | | | | | | | | | | | | | Add a new struct kms_sw_plane which delegate a plane and use it in place of sw_displaytarget. Multiple planes share same underlying kms_sw_displaytarget. v2: - add more check for plane size (Tomasz) v3: - split from larger patch (Emil) v4: - no change from v3 v5: - remove mapped field (Tomasz) v6: - remove change-id in commit message (Tomasz) v7: - add revision history in commit message (Emil) Reviewed-by: Tomasz Figa <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* gallium/winsys/kms: Fix possible leak in map/unmap.Lepton Wu2018-03-221-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If user calls map twice for kms_sw_displaytarget, the first mapped buffer could get leaked. Instead of calling mmap every time, just reuse previous mapping. Since user could map same displaytarget with different flags, we have to keep two different pointers, one for rw mapping and one for ro mapping. Also introduce reference count for mapped buffer so we can unmap them at right time. v2: - avoid duplicated mapping and leaked mapping (Tomasz) v3: - split from larger patch (Emil) v4: - remove munmap from dt_destory (Emil) v5: - introduce reference count for mapping (Tomasz) - add back munmap in dt_destory v6: - remove change-id in commit message (Tomasz) v7: - remove munmap from dt_destory again (Emil) - add revision history in commit message (Emil) Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Tomasz Figa <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* autotools: add tegra header filesJuan A. Suarez Romero2018-03-221-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* ac/surface: compute tile swizzle for GFX9Marek Olšák2018-03-211-0/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
* virgl: resize resource bo allocation if we need to.Dave Airlie2018-03-152-4/+12
| | | | | | | This fixes an illegal command buffer on the host seen with piglit arb_internalformat_query2-max-dimensions Signed-off-by: Dave Airlie <[email protected]>
* tegra: Initial supportThierry Reding2018-03-095-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra K1 and later use a GPU that can be driven by the Nouveau driver. But the GPU is a pure render node and has no display engine, hence the scanout needs to happen on the Tegra display hardware. The GPU and the display engine each have a separate DRM device node exposed by the kernel. To make the setup appear as a single device, this driver instantiates a Nouveau screen with each instance of a Tegra screen and forwards GPU requests to the Nouveau screen. For purposes of scanout it will import buffers created on the GPU into the display driver. Handles that userspace requests are those of the display driver so that they can be used to create framebuffers. This has been tested with some GBM test programs, as well as kmscube and weston. All of those run without modifications, but I'm sure there is a lot that can be improved. Some fixes contributed by Hector Martin <[email protected]>. Changes in v2: - duplicate file descriptor in winsys to avoid potential issues - require nouveau when building the tegra driver - check for nouveau driver name on render node - remove unneeded dependency on libdrm_tegra - remove zombie references to libudev - add missing headers to C_SOURCES variable - drop unneeded tegra/ prefix for includes - open device files with O_CLOEXEC - update copyrights Changes in v3: - properly unwrap resources in ->resource_copy_region() - support vertex buffers passed by user pointer - allocate custom stream and const uploader - silence error message on pre-Tegra124 - support X without explicit PRIME Changes in v4: - ship Meson build files in distribution tarball - drop duplicate driver_tegra dependency Reviewed-by: Emil Velikov <[email protected]> Acked-by: Emil Velikov <[email protected]> Tested-by: Andre Heider <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
* winsys/amdgpu: pad compute IBsMarek Olšák2018-03-081-1/+3
| | | | | | v2: pad with PKT2 NOPs on SI Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-082-2/+4
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* virgl: handle getting new capsets.Dave Airlie2018-03-055-30/+28
| | | | | | | | This checks the kernel api is new enough and asks for the larger caps size since the kernel won't mess it up now. Reviewed-by: Stéphane Marchesin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* winsys/amdgpu: request high addressesChristian König2018-02-281-4/+12
| | | | | | | | | We now have hopefully fixed all bugs regarding high addresses on Vega10 and Raven. Start to use the high range to make room for SVM in the low range. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu:add uvd hevc enc support in amdgpu csJames Zhu2018-02-211-0/+6
| | | | | | | Support UVD HEVC encode in amdgpu cs Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* winsys/radeon: implement and enable 32-bit VM allocationsMarek Olšák2018-02-173-8/+64
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/radeon: add struct radeon_vm_heapMarek Olšák2018-02-173-36/+47
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: enable 32-bit VM allocationsMarek Olšák2018-02-171-1/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* meson: Add Haiku platform support v4Alexander von Gluck IV2018-02-161-0/+29
| | | | Reviewed-by: Dylan Baker <[email protected]>
* meson: define empty variables for libswdri and libswkmsdriDylan Baker2018-02-152-3/+2
| | | | | | | | | | | | | | | This allows these variables to unconditionally included in `link_with` lists, even if they're not used. This allows deleting duplicated logic in nearly every gallium target implemented in meson today. This also removes the now useless `build_by_default` flag from swdri and swkmsdri. v4: - add this patch Fixes: 66c94b9313a697ce8f2b222f4ba353035e4b8726 ("meson: build gallium winsys for dri, null, and wrapper") Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* virgl: Support v2 caps struct (v2)Stéphane Marchesin2018-02-131-1/+37
| | | | | | | | | This struct allows us to report: - accurate max point size/line width. - accurate texel and texture gather offsets - vertex/geometry limits. Signed-off-by: Dave Airlie <[email protected]>
* winsys/amdgpu: allow non page-aligned size bo creation from pointerMichal Navratil2018-02-061-4/+7
| | | | | | | | | Fix INVALID_OPERATION caused by BufferData with target EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD when the buffer size is not page aligned. Signed-off-by: Marek Olšák <[email protected]> Cc: 17.3 18.0 <[email protected]>
* winsys/radeon: Compute is_displayable in surf_drm_to_winsysMichel Dänzer2018-01-311-0/+3
| | | | | | | | It was always 0, breaking (at least) DRI3 with Xwayland. Bugzilla: https://bugs.freedesktop.org/104306 Fixes: 5f2073be3282 ("ac/surface: add ac_surface::is_displayable") Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add support for syncobj signaling v3Andres Rodriguez2018-01-302-1/+86
| | | | | | | | | | Add the ability to signal a syncobj when a cs completes execution. v2: corresponding changes for gallium fence->semaphore rename v3: s/semaphore/fence for pipe objects Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: set number of pb_cache buckets = number of heapsMarek Olšák2018-01-274-33/+25
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* pb_cache: let drivers choose the number of bucketsMarek Olšák2018-01-274-4/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: fix assertion failure with UVD and VCE ringsMarek Olšák2018-01-261-2/+1
| | | | Cc: 18.0 <[email protected]>
* radeonsi: Export signalled sync file instead of -1.Bas Nieuwenhuizen2018-01-261-0/+22
| | | | | | | | -1 is considered an error for EGL_ANDROID_native_fence_sync, so we need to actually create a sync file. Fixes: f536f45250 "radeonsi: implement sync_file import/export" Reviewed-by: Dave Airlie <[email protected]>
* winsys/svga: check correct member after createGrazvydas Ignotas2018-01-231-1/+1
| | | | | | | | | .mob_fenced was already checked, probably a copy-paste bug. Found by Coccinelle. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* autotools: include meson build files in tarballDylan Baker2018-01-1918-5/+31
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/radeon: fix up default enabled_rb_mask for r600Roland Scheidegger2018-01-101-6/+10
| | | | | | | | | | | | | | The logic had two fatal flaws which completely killed the default value. 1) drm will overwrite the value anyway even if the chip can't be handled 2) the default value logic is relying on num_render_backends, which was filled in later. Luckily noone is relying on it, but it's a bit confusing seeing the chip clock printed out there (as hex) with R600_DEBUG=info... (Albeit radeonsi does not appear to fix up the value. If kernels which don't handle this query are still supported, radeonsi will still end up with a broken enabled_rb_mask, I have no idea of the potential results of this there.) Reviewed-by: Dave Airlie <[email protected]>
* winsys/amdgpu: disable local BOs again due to worse performanceMarek Olšák2017-12-111-2/+3
| | | | | Cc: 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: fix pl111 dependency on vc4Eric Engestrom2017-12-071-0/+1
| | | | | | | | src/gallium/winsys/pl111/drm/libpl111winsys.a(pl111_drm_winsys.c.o): In function `pl111_drm_screen_create': pl111_drm_winsys.c:(.text+0x33): undefined reference to `vc4_drm_screen_create_renderonly' Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: fix keyword argument in declare_dependency()Eric Engestrom2017-12-062-2/+2
| | | | | | | | | `declare_dependency()` takes `compile_args`, not `c_args`. It was correct in all the other `declare_dependency()` from that commit. Fixes: 0bbecc5a8548883f76a71 "meson: define driver dependencies" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* winsys/amdgpu: make IBs use read-only memoryMarek Olšák2017-12-061-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: always place sparse buffers in VRAMNicolai Hähnle2017-12-061-2/+3
| | | | | | | | | | | | Together with "radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check", this ensures that sparse buffers are placed in VRAM. Noticed by an assertion that started triggering with commit d4fac1e1d7 ("gallium/radeon: enable suballocations for VRAM with no CPU access") Fixes KHR-GL45.sparse_buffer_tests.BufferStorageTest in debug builds. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* winsys/amdgpu: add RADEON_FLAG_READ_ONLYMarek Olšák2017-12-051-1/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move setting VRAM|GTT into winsysesMarek Olšák2017-12-053-1/+28
| | | | | | The combined VRAM|GTT heap will be removed. Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: define driver dependenciesDylan Baker2017-12-042-0/+10
| | | | | | | | | | | | This allow us to encapsulate the compiler and linkage requirements of each driver in a reusable way. The result will be that each target that needs a specific driver can simply add `driver_<name>` to its dependencies line and the necessary libraries and compiler args will be added. This will allow for a lot of code de-duplication between gallium targets. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* amd: remove always-true BRAHMA_BUILD defineEric Engestrom2017-12-011-3/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*Marek Olšák2017-11-294-8/+8
| | | | | | and handle PIPE_FLUSH_HINT_FINISH in r300. Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: build virgl driverDylan Baker2017-11-282-0/+53
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build svga driver on linuxDylan Baker2017-11-281-0/+45
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build i915g driverDylan Baker2017-11-281-0/+31
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* ac: change legacy_surf_level::slice_size to dword unitsMarek Olšák2017-11-271-2/+2
| | | | | | | | | The next commit will reduce the size even more. v2: typecast to uint64_t manually v3: add more typecasts, add asserts Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add vcn enc cs supportBoyuan Zhang2017-11-171-1/+6
| | | | | | | New cs support is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-134-4/+0
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* meson: build gallium-xlib based glxDylan Baker2017-11-101-0/+27
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fencesNicolai Hähnle2017-11-093-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to fix the following interleaving of operations that can arise from deferred fences: Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = deferred flush <------- application-side synchronization -------> fence_server_sync(f) ... flush() flush() We will now stall in fence_server_sync until the flush of context 1 has completed. This scenario was unlikely to occur previously, because applications seem to be doing Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = glFenceSync() glFlush() <------- application-side synchronization -------> glWaitSync(f) ... and indeed they probably *have* to use this ordering to avoid deadlocks in the GLX model, where all GL operations conceptually go through a single connection to the X server. However, it's less clear whether applications have to do this with other WSI (i.e. EGL). Besides, even this sequence of GL commands can be translated into the Gallium-level sequence outlined above when Gallium threading and asynchronous flushes are used. So it makes sense to be more robust. As a side effect, we no longer busy-wait on submission_in_progress. We won't enable asynchronous flushes on radeon, but add a cs_add_fence_dependency stub anyway to document the potential issue. Reviewed-by: Marek Olšák <[email protected]>
* util: move os_time.[ch] to src/utilNicolai Hähnle2017-11-096-6/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amdgpu: use simple mtxTimothy Arceri2017-11-095-44/+45
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/addrlib: update to latest versionMarek Olšák2017-11-081-1/+0
| | | | | | | | | | | | This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle <[email protected]>
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