| Commit message (Collapse) | Author | Age | Files | Lines |
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SVGA_3D_CMD_DX_GENRATE_MIPMAP & SVGA_3D_CMD_DX_SET_PREDICATION commands
are not presents in fedora 24 kernel module. Because of this
reason application like supertuxkart are not running.
v2: Add few comments and code modifications suggested by Brian P.
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: Charmaine Lee <[email protected]>
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Signed-off-by: sonjiang <[email protected]>
Cc: "12.0" <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
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for a later use
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Vedran Miletić <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <[email protected]>
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This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <[email protected]>
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so that independent types of jobs can use the same queue.
Reviewed-by: Nicolai Hähnle <[email protected]>
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for debugging
v2: correct the snprintf use
Reviewed-by: Nicolai Hähnle <[email protected]>
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independent jobs don't have to be stuck on only one thread
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <[email protected]>
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and allow specifying its size in util_queue_init.
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <[email protected]>
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v2: fixup after renaming to util_queue_fence
Reviewed-by: Nicolai Hähnle <[email protected]>
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v2: rename the event to util_queue_fence
Reviewed-by: Nicolai Hähnle <[email protected]>
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for easier access
Reviewed-by: Nicolai Hähnle <[email protected]>
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Fix warnings like these due to HAVE_LIBDRM being inconsistently defined:
external/libdrm/include/drm/drm.h:839:30: warning: redefinition of typedef 'drm_clip_rect_t' is a C11 feature [-Wtypedef-redefinition]
typedef struct drm_clip_rect drm_clip_rect_t;
HAVE_LIBDRM needs to be set project wide to fix this. This change also
harmlessly links libdrm with everything, but simplifies the makefiles a
bit.
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Emil Velikov <[email protected]>
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When calling virgl_fence_wait() with timeout=0,
virgl_{drm,vtest}_resource_is_busy() is called. However, it returns TRUE
for a busy resource, whereace virgl_fence_wait() should return TRUE for
a completed (non-busy) resource.
This fixes running supertuxkart in a VM (I could not reproduce locally
with vtest though there is a similar fix)
Signed-off-by: Marc-André Lureau <[email protected]>
Cc: "11.1 11.2 12.0" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Also add dcc_fast_clear_size for clearing only the necessary subset
of DCC. For no AA, it's equal to the size of the whole DCC level.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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R9G9B9E5 is the only uncompressed one hopefully.
This fixes incorrect rendering not discovered (due to a lack of tests)
until DCC mipmapping was enabled.
Cc: 11.1 11.2 12.0 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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So that memory use will eventually decrease again after a temporary peak.
Reviewed-by: Marek Olšák <[email protected]>
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As a consequence, CE IB size never triggers a flush anymore.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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We will chain multiple chunks together and will keep pointers to the older
chunks to support IB dumping.
Reviewed-by: Marek Olšák <[email protected]>
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This avoids allocating giant IBs from the outset, especially for CE and DMA.
Since we now limit max_dw only by the size that the buffer happens to be
(which, due to the buffer cache, can be even larger than the rounded-up size
we request), the new function amdgpu_ib_max_submit_dwords controls when we
submit an IB.
With this change, we effectively never flush prematurely due to the CE IB,
after an initial warm-up phase.
v2:
- clean up buffer_size calculation
Reviewed-by: Marek Olšák <[email protected]>
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The latter function allows getting the containing amdgpu_cs from any IB
(including non-main ones).
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Adding the buffer when we start using it for the IB makes the logic for
chaining a bit simpler.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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We'll want to have an amdgpu_cs pointer for future changes.
Reviewed-by: Marek Olšák <[email protected]>
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v2: style change
Reviewed-by: Marek Olšák <[email protected]>
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This mimics Vulkan. It also documents how to fix stencil texturing.
Reviewed-by: Michel Dänzer <[email protected]>
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Push offset down to drivers when importing dmabuf. This is needed
to more fully support EGL_EXT_image_dma_buf_import when a non-zero
offset is specified.
Tesing has been done for freedreno, and compile tested following
gallium drivers:
nouveau,svga,virgl,r600,r300,radeonsi,swrast,i915,ilo
Signed-off-by: Stanimir Varbanov <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
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Ported from the initial amdgpu winsys from the private AMD branch.
The thread creates the buffer list, submits IBs, and cleans up
the submission context, which can also destroy buffers.
3-5% reduction in CPU overhead is expected for apps submitting a lot
of IBs per frame. This is most visible with DMA IBs.
v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs
add another amdgpu_cs_sync_flush call into amdgpu_bo_map
Reviewed-by: Nicolai Hähnle <[email protected]>
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There is no point.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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When user fences are used, we don't need the kernel for polling.
Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Jan Vesely <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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It's for the buffer cache.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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this is a leftover from the days when depth-stencil buffers were
allocated by the DDX
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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This hasn't been needed, but I think we should set it.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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for indexing cik_macrotile_mode_array
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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This will allow us to simplify a lot of code around tiling.
Kernel 3.10 is required for SI support.
Kernel 3.13 is required for CIK support.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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ported from winsys/radeon.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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