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* r600g: disable shader rebuild optimization & account cb flush packetJerome Glisse2010-09-221-1/+9
| | | | | | | | | Shader rebuild should be more clever, we should store along each shader all the value that change shader program rather than using flags in context (ie change sequence like : change vs buffer, draw, change vs buffer, switch shader will trigger useless shader rebuild). Signed-off-by: Jerome Glisse <[email protected]>
* r600g: flush color buffer after draw commandJerome Glisse2010-09-221-1/+36
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* winsys: automatically build sw winsys needed by EGL and d3d1xLuca Barbieri2010-09-221-0/+10
| | | | A cleaner solution would be preferable, but this does no harm and works.
* r600g: occlusion query for new designJerome Glisse2010-09-212-5/+153
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: directly allocate bo for user bufferJerome Glisse2010-09-212-24/+27
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix eg texture borders.Dave Airlie2010-09-212-13/+16
| | | | texture border regs are indexed on evergreen.
* r600g: add back reference check when mapping bufferJerome Glisse2010-09-201-6/+7
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use pipe context for flushing inside mapJerome Glisse2010-09-201-7/+7
| | | | | | | | | This allow to share code path btw old & new, also remove check on reference this might make things a little slower but new design doesn't use reference stuff. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: move chip class to radeon common structureJerome Glisse2010-09-204-0/+74
| | | | | | | So texture code can be shared btw new state design & old one. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: only flush for the correct colorbuffer, not all of them.Dave Airlie2010-09-201-2/+4
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* r600g: fixup r700 CB_SHADER_CONTROL register.Dave Airlie2010-09-201-1/+1
| | | | r600c emits this with a mask of each written output.
* r600g: fix tiling support for ddx supplied buffersDave Airlie2010-09-201-9/+9
| | | | needed to emit some more relocs to the kernel.
* r600g: send correct surface base update for multi-cbufsDave Airlie2010-09-201-2/+4
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* r600g: Respect PB_USAGE_UNSYNCHRONIZED in radeon_bo_pb_map_internal().Henri Verbeet2010-09-191-0/+8
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* r600g: Buffer object maps imply a wait.Henri Verbeet2010-09-192-18/+13
| | | | Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
* r600g: Check for other references before checking for existing mappings in ↵Henri Verbeet2010-09-191-6/+8
| | | | | | | radeon_bo_pb_map_internal(). Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping, it may have been unmapped but not flushed yet.
* r600g: Silence uninitialized variable warning.Vinson Lee2010-09-171-1/+2
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* r600g: Fix memory leak on error path.Vinson Lee2010-09-171-1/+1
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* r600g: Fix implicit declaration warning.Vinson Lee2010-09-171-0/+1
| | | | | | Fixes this GCC warning. r600_state2.c: In function 'r600_context_flush': r600_state2.c:946: error: implicit declaration of function 'drmCommandWriteRead'
* r600g: Remove unnecessary headers.Vinson Lee2010-09-171-3/+0
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* r600g: alternative command stream building from contextJerome Glisse2010-09-175-9/+1310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: oops got the use_mem_constant the wrong way around.Dave Airlie2010-09-181-1/+1
| | | | this fixes evergreen gears again.
* r600g: use calloc for ctx bo allocationsDave Airlie2010-09-171-1/+1
| | | | since the reference code relies on these being NULL.
* r600g: fixup map flushing.Dave Airlie2010-09-171-5/+9
| | | | | | long lived maps were getting removed when they shouldn't this tries to avoid that problem by only adding to the flush list on unmap.
* r600g: add winsys bo caching.Dave Airlie2010-09-174-31/+24
| | | | | | | this adds the bo caching layer and uses it for vertex/index/constant bos. ctx needs to take references on hw bos so the flushing works okay, also needs to flush the maps.
* r600g: add support for kernel boDave Airlie2010-09-178-50/+344
| | | | this moves to using a pb bufmgr instead of kernel bos directly.
* r600g: use malloc bufmgr for constant buffersDave Airlie2010-09-173-1/+9
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* r600g: move constant buffer creation behind winsys abstraction.Dave Airlie2010-09-174-10/+42
| | | | this paves the way for moving to pb bufmgrs now.
* r600g: attempt to abstract kernel bos from pipe driver.Dave Airlie2010-09-178-72/+140
| | | | | | introduce an abstraction layer between kernel bos and the winsys BOs. this is to allow plugging in pb manager with minimal disruption to pipe driver.
* r600g: hide radeon_ctx inside winsys.Dave Airlie2010-09-172-8/+20
| | | | no need for this info to be exported to pipe driver.
* r300g: fix buffer reuse issue caused by previous commitDave Airlie2010-09-151-3/+6
| | | | | | caused by 0b9eb5c9bb03e5134d9a41786178100109e80c5a test run glxgears, resize.
* r300g: prevent creating multiple winsys BOs for the same handleMarek Olšák2010-09-151-0/+26
| | | | | | | This fixes a DRM deadlock in the cubestorm xscreensaver, because somehow there must not be 2 different BOs relocated in one CS if both BOs back the same handle. I was told it is impossible to happen, but apparently it is not, or there is something else wrong.
* r300g: fix map_bufferMarek Olšák2010-09-131-4/+17
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=30145
* pb: add void * for flush ctx to mapping functionsDave Airlie2010-09-122-8/+4
| | | | | | | | | | If the buffer we are attempting to map is referenced by the unsubmitted command stream for this context, we need to flush the command stream, however to do that we need to be able to access the context at the lowest level map function, currently we set the buffer in the toplevel map, but this racy between context. (we probably have a lot more issues than that.) I'll look into a proper solution as suggested by jrfonseca when I get some time.
* r600g: Only increase a bo's map_count if radeon_bo_map() succeeded.Tilman Sauerbeck2010-09-101-2/+6
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Fixed a bo leak in the error path of radeon_ctx_set_bo_new().Tilman Sauerbeck2010-09-101-2/+1
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: fixup state calculations for picking states.Dave Airlie2010-09-106-29/+15
| | | | | for evergreen I ended up using a non-contig array of states, but this code needs a bit of fixing up to deal with that.
* r600g: evergreen CBs are more sane to support with a single stateDave Airlie2010-09-102-81/+2
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* r600g: add multi-buffer flush support properly.Dave Airlie2010-09-101-6/+7
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* r600g: fix regression in multi-buffer tests since CB flush mergeDave Airlie2010-09-101-14/+14
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* r600g: add initial evergreen supportDave Airlie2010-09-105-22/+755
| | | | | | | | | | adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
* r600g: align flushing of cb/db with DDX/r600c.Dave Airlie2010-09-102-32/+35
| | | | | | | | | the DDX and r600c both flush cb/db after the draw is emitted, as long as they do that, r600g can't be different, as it races. We end up with r600g flush, set CB, DDX set CB, flush. This was causing misrendering on my evergreen, where sometimes the drawing would go to an old CB.
* r600g: don't need 3 bos here.Dave Airlie2010-09-101-2/+2
| | | | the code should reloc correctly a single BO 3 times.
* winsys: emit warning in null_sw_displaytarget_create()Brian Paul2010-09-091-0/+2
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* r600g: add support for constants in memory buffers.Dave Airlie2010-09-082-0/+11
| | | | | | DX9 constants were in the constant file, and evergreen no longer support cfile. r600/700 can also use constants in memory buffers, so add the code (disabled for now) to enable that as precursor for evergreen.
* r600g: add script to generate header file with offsets into state objects.Dave Airlie2010-09-061-0/+39
| | | | | | | | This was inherently fragile as any changes to r600_states.h would also need manual updating of all of the bits in radeon.h. Just add a simple python script to do the conversion, its not hooked up to make at all. This also will make adding evergreen a bit easier.
* r600g: force unbind of previously bind sampler/sampler_viewJerome Glisse2010-09-021-3/+0
| | | | | | | | | | | | | | | | Previously bind sampler/sampler_view can be converted and endup overwritting the current state we want to schedule. Example : bind texA texB to sampler_view[0] & sampler_view[1], render, bind texB to sampler_view[0] render. Now state associated to texB are set to configure sampler_view slot 0, but as we don't unbind sampler_view[1] still point to texB state so we end up with sampler_view[1] overwritting sampler_view[0], which gives wrong rendering if next rendering bind texA to sampler_view[0], it will endup as texB is bound to sampler_view[0]. If you are not confuse at that point give me a call i will be buying you beer. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix memory/bo leakJerome Glisse2010-09-021-2/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: avoid dynamic allocation of statesJerome Glisse2010-09-016-308/+122
| | | | | | | | | | | Make state statically allocated, this kills a bunch of code and avoid intensive use of malloc/free. There is still a lot of useless duplicate function wrapping that can be kill. This doesn't improve yet performance, needs to avoid memcpy states in radeon_ctx_set_draw and to avoid rebuilding vs_resources, dsa, scissor, cb_cntl, ... states at each draw command. Signed-off-by: Jerome Glisse <[email protected]>
* Revert "Revert "r600g: precompute some of the hw state""Jerome Glisse2010-09-014-32/+87
| | | | | | | | This reverts commit 1fa7245c348cb7aced81f1672140f64cb6450e2f. Conflicts: src/gallium/drivers/r600/r600_state.c
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