| Commit message (Collapse) | Author | Age | Files | Lines |
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Spotted by Henri on IRC.
Signed-off-by: Alex Deucher <[email protected]>
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This packet is required when updating the DB, CB,
or STRMOUT base addresses on rv6xx for the surface
sync logic to work correctly.
Signed-off-by: Alex Deucher <[email protected]>
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The drivers have been changed so that they behave as if all of the flags
were set. This is already implicit in most hardware drivers and required
for multiple contexts.
Some state trackers were also abusing the PIPE_FLUSH_RENDER_CACHE flag
to decide whether flush_frontbuffer should be called.
New flag ST_FLUSH_FRONT has been added to st_api.h as a replacement.
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This fd gets passed in from outside, closing it causes the X.org server
to crap out when the driver doesn't identify the chipset.
Signed-off-by: Dave Airlie <[email protected]>
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The build still fails.
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Thread offloading is not sometimes desirable, e.g. when mapping a buffer.
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Running any older kernel is not recommended anyway.
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No one ever cared. libdrm does dynamic resizing of its reloc-table,
anyway.
Signed-off-by: Daniel Vetter <[email protected]>
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This is reliant on a drm patch that I posted on the list + a version bump.
These will appear in drm-next today.
Signed-off-by: Dave Airlie <[email protected]>
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If the drm minor version is > 9 (i.e. whats in drm-next),
we enable s3tc + texture tiling by default now.
this changes R600_FORCE_TILING to R600_TILING which can
be set to false to disable tiling on working drm.
Signed-off-by: Dave Airlie <[email protected]>
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v2: Add the batch bo to the libdrm validation lost, for otherwise
libdrm won't take previously used buffers into account.
Signed-off-by: Daniel Vetter <[email protected]>
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These files can be decoded with intel_dump_decode from the intel-gpu-tools
available at:
http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/
Signed-off-by: Daniel Vetter <[email protected]>
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platform.system in SCons on Cygwin includes the OS version number.
Windows XP - CYGWIN_NT-5.1
Windows Vista - CYGWIN_NT-6.0
Windows 7 - CYGWIN_NT-6.1
Reduce all Cygwin platform variants to just 'cygwin' so anything
downstream can simply use 'cygwin' instead of the different full
platform names.
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Fixes immediate Python exceptions with SCons on Cygwin.
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Intel classic drivers switched to this, too, so it must be good.
Signed-off-by: Daniel Vetter <[email protected]>
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Signed-off-by: Daniel Vetter <[email protected]>
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We're using bo_subdata.
Signed-off-by: Daniel Vetter <[email protected]>
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radeon_bo_unref may destroy the buffer, so call it after p_atomic_dec, not before.
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This is a multi-threading optimization which hides the kernel overhead
behind a thread. It improves performance in CPU-limited apps by 2-15%.
Of course you must have at least 2 cores for it to make any difference.
It can be disabled with:
export RADEON_THREAD=0
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Ooops.
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The VBO module uses both, but they are somewhat opposite to each other.
In this case, we pick UNSYNCHRONIZED and ignore DONTBLOCK.
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This is the last one I think.
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Because an app may do something like this:
while (!(ptr = bo_map(..., DONT_BLOCK))) {
/* Do some other work. */
}
And it would be looping endlessly if we didn't flush.
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Accidentally negated in 685c3262b945a7f0e9f1f3a9409a12fdda08c828.
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This should prevent calling into radeon_get_reloc when there's
only one context.
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We don't need the read/write flags.
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Based on Dave's branch.
The majority of this commit is a cleanup, mainly renaming things.
There wasn't much code to import, just ioctl calls.
Also done:
- implemented unsynchronized bo_map (important optimization!)
- radeon_bo_is_referenced_by_cs is no longer a refcount hack
- dropped the libdrm_radeon dependency
I'm surprised that this has resulted in less code in the end.
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Exactly one half would be the ideal, but this is a soft limit, and one
more byte over brings us to synchronous behavior.
Flushing when the referred GMR exceeds one third of the aperture gives us
statistically better performance.
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If we see a MACRO bit on r600g its 2D tiled,
if don't see a MACRO bit and we do see a MICRO bit then its 1D tiled.
Signed-off-by: Dave Airlie <[email protected]>
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this just adds the ioctl interface and sets the tile type
and array mode in the correct place.
This seems to bring eg 1D tiling to the same level, and issues
as on r600. No idea how to address 2D yet.
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Print warnings and continue build.
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the context init is separate for these gpus.
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6xx/7xx have a max of 4 DBs, evergreen have a max of 8.
Signed-off-by: Alex Deucher <[email protected]>
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Like on some r5xx, there are multiple DB backends on the r600,
we need to add up the query results from each of these to get the
final correct value.
So far I'm not 100% sure how to calculate the num_db, value
setting it to 4 should be harmless enough until we do.
This fixes occulsion_query piglit test on my rv740.
Signed-off-by: Dave Airlie <[email protected]>
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