| Commit message (Collapse) | Author | Age | Files | Lines |
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This makes Tonga with vramlimit=128 2x faster in Heaven.
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
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A better solution will be used.
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
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print as unsigned instead of signed
Reviewed-by: Nicolai Hähnle <[email protected]>
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v2: fail in radeon_winsys_bo_create if size > 32 bits
Reviewed-by: Nicolai Hähnle <[email protected]>
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being able to allocate more than 4 GB may be useful
Reviewed-by: Nicolai Hähnle <[email protected]>
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v2: Polaris chips should be defined after Stoney
Signed-off-by: Sonny Jiang <[email protected]> (v1)
Reviewed-by: Michel Dänzer <[email protected]> (v1)
Signed-off-by: Leo Liu <[email protected]> (v2 diff)
Reviewed-by: Alex Deucher <[email protected]> (v2 diff)
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v2: fix indentation as noted by Michel
Signed-off-by: Sonny Jiang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Cons:
- it was only integrated in r600g
- it doesn't work with GPUVM
- it records buffer contents at the end of IBs instead of at the beginning,
so the replay isn't exact
- it lacks an IB parser and user-friendliness
A better solution is apitrace in combination with gallium/ddebug, which
has a complete IB parser and can pinpoint hanging CP packets.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Add layer support to export individual array layers.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Add offset support to handle NV12 offsets as well.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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We are going to need this for EGL_EXT_image_dma_buf_import.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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This will be queried by the OpenCL stack using an interop call.
I have tested that the values match lspci.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags
in IBs.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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and call it radeon_bo_metadata
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This will allow drivers to make better decisions about texture sharing
for DRI2, DRI3, Wayland, and OpenCL.
v2: add read/write flags, take advantage of __DRI_IMAGE_USE_BACKBUFFER
Reviewed-by: Axel Davy <[email protected]>
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Enlarge the buffer hashlist to prevent large numbers of misses
due to adding more buffers than can be cached in the hashlist.
The game I tested had CS's with up to 1500 buffers and the overhead
of amdgpu_lookup_buffer for various sizes was:
4096 1.97% (new value)
2048 4.37%
1024 6.92%
512 9.47% (old value)
(percentage of CPU usage in render thread as determined by perf)
The time spent in amdgpu_add_buffer self is ~4.2% in all cases and
for 4096 the time needed to clear the hashlist is still < 0.10%,
so I am not expecting significant regressions.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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To ask how large the current command buffer is. Will be used for
a new GALLIUM_HUD graph.
Reviewed-by: Charmaine Lee <[email protected]>
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If running with a software renderer backend, the timeout may be
insufficient, and we don't want to release busy buffers too early.
In practice, SVGA gpu lockups are extremely rare.
Signed-off-by: Thomas Hellstrom <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
Cc: "11.0 11.1" <[email protected]>
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Reported-by: Brian Paul <[email protected]>
Signed-off-by: Thomas Hellstrom <[email protected]>
Reviwed-by: Brian Paul <[email protected]>
Cc: "11.0 11.1" <[email protected]>
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in order to make some winsys interface changes easier
This distros should use new DRM if they want to use new Mesa:
Distro kernel mesa eol
SLES 10 2.6.16 6.4.2 2016-07
SLED 11 3.0 9.0.3 2022-03
RHEL 5 2.6.18 6.5.1 2017-03
RHEL 6 2.6.32 10.4.3 2020-11
Debian 6 2.6.32 7.7.1 2016-02
Reviewed-by: Michel Dänzer <[email protected]>
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Signed-off-by: Ben Skeggs <[email protected]>
Acked-by: Ilia Mirkin <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
v2: adjust the comment in the amdgpu winsys
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v2: Clarify the relation between num_tiles_pipes and GB_TILE_MODE and the fix
needed for Tahiti as suggested by Marek.
Signed-off-by: Alexandre Demers <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94019
Tested-by: Nick Sarnie <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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amdgpu doesn't have to set this, because radeonsi gets it from tile mode
arrays by default.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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v2: print an error to stderr
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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This fixes a crash in pb_cache_release_all_buffers.
Signed-off-by: Niels Ole Salscheider <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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This is fallout from the previous changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93961
Signed-off-by: Dave Airlie <[email protected]>
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Enabling swrast on Android causes a link error because vtest is missing.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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The virgl reference counting of buffers is broken for prime fd buffers.
Each prime fd passed into virgl_drm_winsys_resource_create_handle creates
a new resource. The solution requires creating a separate hash table to
track flink names separately from prime handles.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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It is necessary to share the screen between mesa and gralloc to
properly ref count resources. This implements a hash lookup on
the file description to re-use an already created screen. This is
a similar implementation as freedreno and radeon.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created
in VRAM if they get evicted to GTT. In general there's no need to
restrict any of the flags to any particular domains.
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to tiled BOs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862
(This change shouldn't be backported to stable branches, because
released versions of xf86-video-amdgpu unnecessarily try to map the
front buffer)
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Set RADEON_ALL_BOS=1 to use it.
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This is just a copy-n-paste and rename of vc4 Android makefiles.
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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radeon sets this correctly, but not amdgpu
Reviewed-by: Nicolai Hähnle <[email protected]>
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The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.
Reviewed-by: Marek Olšák <[email protected]>
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Some confusion between pb_buffer and radeon_bo as well as between
radeon_drm_winsys and radeon_winsys.
Reviewed-by: Marek Olšák <[email protected]>
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Rename SVGA_HINT_FLAG_DRAW_EMITTED to SVGA_HINT_FLAG_CAN_PRE_FLUSH
because preemptive flush can be unblocked by more commands than
draw.
Reviewed-by: Brian Paul <[email protected]>
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Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Tested-by: Samuel Pitoiset <[email protected]>
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