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* r600g: fix pointsprite & resource unbindingJerome Glisse2010-09-272-14/+40
| | | | | | | | | | When asking to bind NULL resource assume it's unbinding so free resource and unreference assoicated buffer. Also fix pointsprite parameter. Fix glsl-fs-pointcoord & fp-fragment-position Signed-off-by: Jerome Glisse <[email protected]>
* r600g: build packet header onceJerome Glisse2010-09-272-85/+160
| | | | | | | | Build packet header once and allow to add fake register support so we can handle things like indexed set of register (evergreen sampler border registers for instance. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add evergreen texture resource properly.Dave Airlie2010-09-271-3/+109
| | | | adding sampler border looks impossible with current design, another day, another corner case not worked out.
* radeong: fix leaksJoakim Sindholt2010-09-261-0/+3
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* r600g: disable early cull optimization when occlusion query runningJerome Glisse2010-09-264-0/+60
| | | | | | | | | | When occlusion query are running we want to have accurate fragment count thus disable any early culling optimization GPU has. Based on work from Bas Nieuwenhuizen <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: Include p_compiler.h instead of malloc.h.Vinson Lee2010-09-261-1/+1
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* r600g: Remove unused variables.Vinson Lee2010-09-261-1/+1
| | | | | | | | | Fixes these GCC warnings. radeon.c: In function 'radeon_new': radeon.c:59: warning: unused variable 'k' radeon.c:59: warning: unused variable 'j' radeon.c:59: warning: unused variable 'id' radeon.c:59: warning: unused variable 'i'
* r600g: Don't return a value in function returning void.Vinson Lee2010-09-261-1/+1
| | | | | | Fixes this GCC warning. radeon_state.c: In function 'radeon_state_fini': radeon_state.c:140: warning: 'return' with a value, in function returning void
* r600g: Remove unused variable.Vinson Lee2010-09-251-1/+0
| | | | | | Fixes this GCC warning. radeon_bo_pb.c: In function 'radeon_bo_pb_create_buffer': radeon_bo_pb.c:178: warning: unused variable 'domain'
* r600g: add eg db count control register.Dave Airlie2010-09-251-0/+1
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* r600g: bring over fix from old path to new pathJerome Glisse2010-09-241-10/+39
| | | | | | | | | | Up to 2010-09-19: r600g: fix tiling support for ddx supplied buffers 9b146eae2521d8e5f6d3cbefa4f6f7737666313a user buffer seems to be broken... new to fix that. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix evergreen new pathJerome Glisse2010-09-241-3/+10
| | | | | | glxgears seems to work, had somelockup but now they seems to have vanish. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix evergreen new pathJerome Glisse2010-09-242-13/+15
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: evergreen fix for new designJerome Glisse2010-09-243-40/+23
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: move use_mem_constants flags for new designs structure alignmentJerome Glisse2010-09-241-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix typo in evergreen define (resource are in [0x30000;0x34000] range)Jerome Glisse2010-09-241-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r300g: make accessing map_list and buffer_handles thread-safeMarek Olšák2010-09-241-6/+58
| | | | NOTE: This is a candidate for the 7.9 branch.
* r300g: fixup long-lived BO maps being incorrectly unmapped when flushingMarek Olšák2010-09-241-4/+10
| | | | | | Based on commit 3ddc714b20ac4e28b80c6f88d1993445fff2262c by Dave Airlie. NOTE: This is a candidate for the 7.9 branch.
* r600g: initial evergreen support in new pathJerome Glisse2010-09-233-11/+707
| | | | | | This doesn't work yet. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix typo in evergreen register listDave Airlie2010-09-231-1/+1
| | | | pointed out by glisse on irc.
* r600g: disable shader rebuild optimization & account cb flush packetJerome Glisse2010-09-221-1/+9
| | | | | | | | | Shader rebuild should be more clever, we should store along each shader all the value that change shader program rather than using flags in context (ie change sequence like : change vs buffer, draw, change vs buffer, switch shader will trigger useless shader rebuild). Signed-off-by: Jerome Glisse <[email protected]>
* r600g: flush color buffer after draw commandJerome Glisse2010-09-221-1/+36
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* winsys: automatically build sw winsys needed by EGL and d3d1xLuca Barbieri2010-09-221-0/+10
| | | | A cleaner solution would be preferable, but this does no harm and works.
* r600g: occlusion query for new designJerome Glisse2010-09-212-5/+153
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: directly allocate bo for user bufferJerome Glisse2010-09-212-24/+27
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix eg texture borders.Dave Airlie2010-09-212-13/+16
| | | | texture border regs are indexed on evergreen.
* r600g: add back reference check when mapping bufferJerome Glisse2010-09-201-6/+7
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use pipe context for flushing inside mapJerome Glisse2010-09-201-7/+7
| | | | | | | | | This allow to share code path btw old & new, also remove check on reference this might make things a little slower but new design doesn't use reference stuff. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: move chip class to radeon common structureJerome Glisse2010-09-204-0/+74
| | | | | | | So texture code can be shared btw new state design & old one. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: only flush for the correct colorbuffer, not all of them.Dave Airlie2010-09-201-2/+4
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* r600g: fixup r700 CB_SHADER_CONTROL register.Dave Airlie2010-09-201-1/+1
| | | | r600c emits this with a mask of each written output.
* r600g: fix tiling support for ddx supplied buffersDave Airlie2010-09-201-9/+9
| | | | needed to emit some more relocs to the kernel.
* r600g: send correct surface base update for multi-cbufsDave Airlie2010-09-201-2/+4
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* r600g: Respect PB_USAGE_UNSYNCHRONIZED in radeon_bo_pb_map_internal().Henri Verbeet2010-09-191-0/+8
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* r600g: Buffer object maps imply a wait.Henri Verbeet2010-09-192-18/+13
| | | | Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
* r600g: Check for other references before checking for existing mappings in ↵Henri Verbeet2010-09-191-6/+8
| | | | | | | radeon_bo_pb_map_internal(). Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping, it may have been unmapped but not flushed yet.
* r600g: Silence uninitialized variable warning.Vinson Lee2010-09-171-1/+2
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* r600g: Fix memory leak on error path.Vinson Lee2010-09-171-1/+1
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* r600g: Fix implicit declaration warning.Vinson Lee2010-09-171-0/+1
| | | | | | Fixes this GCC warning. r600_state2.c: In function 'r600_context_flush': r600_state2.c:946: error: implicit declaration of function 'drmCommandWriteRead'
* r600g: Remove unnecessary headers.Vinson Lee2010-09-171-3/+0
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* r600g: alternative command stream building from contextJerome Glisse2010-09-175-9/+1310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: oops got the use_mem_constant the wrong way around.Dave Airlie2010-09-181-1/+1
| | | | this fixes evergreen gears again.
* r600g: use calloc for ctx bo allocationsDave Airlie2010-09-171-1/+1
| | | | since the reference code relies on these being NULL.
* r600g: fixup map flushing.Dave Airlie2010-09-171-5/+9
| | | | | | long lived maps were getting removed when they shouldn't this tries to avoid that problem by only adding to the flush list on unmap.
* r600g: add winsys bo caching.Dave Airlie2010-09-174-31/+24
| | | | | | | this adds the bo caching layer and uses it for vertex/index/constant bos. ctx needs to take references on hw bos so the flushing works okay, also needs to flush the maps.
* r600g: add support for kernel boDave Airlie2010-09-178-50/+344
| | | | this moves to using a pb bufmgr instead of kernel bos directly.
* r600g: use malloc bufmgr for constant buffersDave Airlie2010-09-173-1/+9
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* r600g: move constant buffer creation behind winsys abstraction.Dave Airlie2010-09-174-10/+42
| | | | this paves the way for moving to pb bufmgrs now.
* r600g: attempt to abstract kernel bos from pipe driver.Dave Airlie2010-09-178-72/+140
| | | | | | introduce an abstraction layer between kernel bos and the winsys BOs. this is to allow plugging in pb manager with minimal disruption to pipe driver.
* r600g: hide radeon_ctx inside winsys.Dave Airlie2010-09-172-8/+20
| | | | no need for this info to be exported to pipe driver.
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