| Commit message (Collapse) | Author | Age | Files | Lines |
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This just reduces code size a bit for this chunk.
Signed-off-by: Dave Airlie <[email protected]>
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At the end of flushing we were scanning over 450 blocks
with generally about 50 enabled. This reduces the scanning
to just the list of enabled blocks.
Signed-off-by: Dave Airlie <[email protected]>
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There isn't much point taking the overhead of range/block lookups on resources
we aren't going to be getting resource registers at wierd offsets.
Signed-off-by: Dave Airlie <[email protected]>
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This just splits this function up as pre-cursor to reusing
the internals of it.
Signed-off-by: Dave Airlie <[email protected]>
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resource setting could be a fair bit more lightweight,
this patch just separates the resource structs from the standard
reg tracking structs in the driver, later patches will improve
the winsys.
Signed-off-by: Dave Airlie <[email protected]>
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we don't need to loop over all the registers unless we have
some bos in the block, also avoid setting the ctx flags,
and move the optional stuff down below this chunk.
Signed-off-by: Dave Airlie <[email protected]>
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also fix a unneeded dirty check and add a dirty check speedup.
Signed-off-by: Dave Airlie <[email protected]>
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This moves the overhead of working out the range/block to state build time,
it also allows the compiler to use constants for a lot of things instead
of working them out each time.
Signed-off-by: Dave Airlie <[email protected]>
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this is just an precursor change for some later patches.
Signed-off-by: Dave Airlie <[email protected]>
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These aren't used anymore.
Signed-off-by: Dave Airlie <[email protected]>
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This just avoids copying stuff if its going to modify the number of dwords
later anyways.
Signed-off-by: Dave Airlie <[email protected]>
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This range was 76 dwords long, the 75th dword changes, the first 60 or so
don't. split the block so it emits less often.
Signed-off-by: Dave Airlie <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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- all asics need to emit CONTEXT_CONTROL
- all r6xx asics need to emit 3D_START_CMDBUF
The ddx and r600c already do this. r600g should as well.
Signed-off-by: Alex Deucher <[email protected]>
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On my original R600 card this at least lets gnome shell run for a while longer
and the piglit r300-readcache test case works a lot more reliably.
Still a few more stability issues running a piglit test run though.
Signed-off-by: Dave Airlie <[email protected]>
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The original R600 doesn't have these so don't emit them.
Signed-off-by: Dave Airlie <[email protected]>
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Cayman is the RadeonHD 69xx series of GPUs. This adds support for
3D acceleration to the r600g driver.
Major changes:
Some context registers moved around - mainly MSAA and clipping/guardband related.
GPR allocation is all dynamic
no vertex cache - all unified in texture cache.
5-wide to 4-wide shader engines (no scalar or trans slot)
- some changes to how instructions are placed into slots
- removal of END_OF_PROGRAM bit in favour of END flow control clause
- no vertex fetch clause - TC accepts vertex or texture
Signed-off-by: Dave Airlie <[email protected]>
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If we do this for CB bases then we should do it for DB bases.
noticed while adding cayman support.
Signed-off-by: Dave Airlie <[email protected]>
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this is taken from a patch from Mathias Froehlich, just going to
stage it in a few pieces.
Signed-off-by: Dave Airlie <[email protected]>
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We only need to do this when the texture and CB are using the
same memory area.
Signed-off-by: Dave Airlie <[email protected]>
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We ask for Hyper-Z access when clearing a zbuffer.
We release it if no zbuffer clear has been done for 2 seconds.
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should fix https://bugs.freedesktop.org/show_bug.cgi?id=37157
Signed-off-by: Dave Airlie <[email protected]>
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this just makes the code a little bit cleaner.
Signed-off-by: Dave Airlie <[email protected]>
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only allocate the blocks ptr in the range if we ever have one,
otherwise don't bother wasting the memory.
valgrind glxinfo
before:
==967== in use at exit: 419,754 bytes in 706 blocks
==967== total heap usage: 3,552 allocs, 2,846 frees, 3,550,131 bytes allocated
after:
==5227== in use at exit: 419,754 bytes in 706 blocks
==5227== total heap usage: 3,452 allocs, 2,746 frees, 3,140,531 bytes allocate
Signed-off-by: Dave Airlie <[email protected]>
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This drops 6k of the text segment, a minor drop in the ocean, however
it also makes the code a lot cleaner and removes a lot of duplicated
information, hopefully making it more maintainable.
Signed-off-by: Dave Airlie <[email protected]>
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This table covered a large range unnecessarily, reduce the address
range covered, use the fact that the bottom two bits aren't significant,
and remove unused fields from the range struct. It also drops the hash_size/shift in context in favour of a define, which should make doing the math
a bit less CPU intensive.
valgrind glxinfo
Before:
==320== in use at exit: 419,754 bytes in 706 blocks
==320== total heap usage: 3,691 allocs, 2,985 frees, 7,272,467 bytes allocated
After:
==967== in use at exit: 419,754 bytes in 706 blocks
==967== total heap usage: 3,552 allocs, 2,846 frees, 3,550,131 bytes allocated
Signed-off-by: Dave Airlie <[email protected]>
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Currently r600g always maps every bo, this is quite pointless as it wastes
VM and on 32-bit with wine running VM space is quite useful.
So with this patch we don't create the mappings until first use, without
tiling enabled this probably won't make a major difference on its own,
but with tiled staged uploads it should avoid keeping maps for most of the
textures unnecessarily.
v2: add bo data ptr check
Signed-off-by: Dave Airlie <[email protected]>
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They need the same hack as rv670.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=35312
Signed-off-by: Alex Deucher <[email protected]>
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Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=36914
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Kostas Georgiou <[email protected]>
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Don't emit sync packets for additional CBs or DB.
Spotted by Fredrik Höglund.
Signed-off-by: Alex Deucher <[email protected]>
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Hopefully we can find out the proper fix for this, but for now
this makes the fbo mipmap tests pass on my rv670 (x2 card).
Signed-off-by: Dave Airlie <[email protected]>
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r6xx asics have some problems with the surface
sync logic for the CB and DB. It's recommended
to use the event write interface for flushing
the DB/CB caches rather than the sync packets.
A single event write flush flushes all dst
caches, so we only need one for all CBs and DB.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=35312
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This seems more in line with what the documentation suggests we should be
doing. It doesn't fix the rv635 regression, though I thought it might,
so it means I've no idea whats actually going wrong there.
Signed-off-by: Dave Airlie <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Reported by dir1212 on irc.
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Seems to be a copy-paste bug.
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reinstate b7617346dcff50a66a10c61b95c33682cf629c9e after the
rework in 6067a2a67f9a7aab2aee051469bea8af03747a95.
Signed-off-by: Alex Deucher <[email protected]>
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Keep track of when the caches are dirty, and only flush them when
the framebuffer state is set and when the context is flushed.
Signed-off-by: Dave Airlie <[email protected]>
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this needs revisiting, we really don't want to be flushing all 32 of these,
but currently we don't flush any of them, and it seems to have caused a regression
as reported on irc with doom3 on evergreen.
Signed-off-by: Dave Airlie <[email protected]>
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just makes the code more consistent.
Signed-off-by: Dave Airlie <[email protected]>
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really at these sort of sizes these are pointless inlines.
Signed-off-by: Dave Airlie <[email protected]>
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These really didn't have much difference, and totally not inline material.
Signed-off-by: Dave Airlie <[email protected]>
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Merging the flushes that are left doesn't seem to give a significant
performance improvement
Signed-off-by: Dave Airlie <[email protected]>
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This just avoids reemitting resources that haven't changed.
Signed-off-by: Dave Airlie <[email protected]>
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This gets me from 2200 to 1978 dwords for a gears frame.
This is due to us having some 32-dwords blocks in the SPI, that we only
modify the first dwords off.
v2: fix dirty reg count from Bas Nieuwenhuizen
Signed-off-by: Dave Airlie <[email protected]>
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