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* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-172-30/+17
* ac: add radeon_info::is_amdgpu instead of checking drm_major == 3Marek Olšák2019-06-141-0/+1
* virgl: Return immediately when finding a compatible resource in the cacheAlexandros Frantzis2019-06-141-25/+14
* virgl: Use virgl_resource_cache in the vtest winsysAlexandros Frantzis2019-06-144-122/+44
* virgl: Use virgl_resource_cache in the drm winsysAlexandros Frantzis2019-06-144-123/+44
* virgl: Introduce virgl_resource_cacheAlexandros Frantzis2019-06-145-0/+330
* gallium/winsys/kms: Fix dumb buffer bppKevin Strasser2019-06-121-1/+1
* r300g: restore performance after RADEON_FLAG_NO_INTERPROCESS_SHARING was addedRichard Thier2019-06-111-1/+3
* virgl: consider newly created resources idleChia-I Wu2019-06-111-6/+8
* virgl: make resource_wait/resource_is_busy cheaperChia-I Wu2019-06-112-0/+27
* virgl: add virgl_drm_{alloc,free,clear}_res_listChia-I Wu2019-06-111-17/+42
* virgl: do not cache external resourcesChia-I Wu2019-06-112-1/+10
* virgl: Make VIRGL_BIND_STAGING resources cacheableAlexandros Frantzis2019-06-072-2/+4
* virgl: Deduplicate checks for resource cachingAlexandros Frantzis2019-06-074-20/+14
* virgl: Don't try to use cached resources for legacy fencesAlexandros Frantzis2019-06-072-6/+12
* winsys/svga/drm: Fix 32-bit RPCI send messageDeepak Rawat2019-06-061-12/+23
* winsys/drm: Fix out of scope variable usageDeepak Rawat2019-06-021-12/+13
* build: Build etnaviv drmGuido Günther2019-06-051-2/+4
* amd/common: use generated register headerNicolai Hähnle2019-06-032-2/+1
* radeonsi: clean up winsys creationMarek Olšák2019-05-271-8/+0
* ac: treat Mullins as Kabini, remove the enumMarek Olšák2019-05-271-3/+0
* svga: Add an environment variable to force coherent surface memoryThomas Hellstrom2019-05-174-3/+18
* pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flagsThomas Hellstrom2019-05-171-16/+7
* winsys/svga: Fix RELOC_INTERNAL mob GPU accessThomas Hellstrom2019-05-171-1/+9
* svga: Remove the surface_invalidate winsys functionThomas Hellstrom2019-05-173-18/+0
* r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2019-05-162-8/+0
* winsys/radeon: implement ctx_query_reset_status by copying radeonsiMarek Olšák2019-05-164-6/+43
* winsys/amdgpu: report a CS rejection as a reset only if there's no GPU resetMarek Olšák2019-05-161-6/+5
* winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_spaceMarek Olšák2019-05-162-8/+15
* winsys/amdgpu: add a parallel compute IB coupled with a gfx IBMarek Olšák2019-05-163-5/+160
* winsys/amdgpu: always set NO_CPU_ACCESS and NO_SUBALLOC on GDS resourcesMarek Olšák2019-05-161-2/+5
* ac: rename SI-CIK-VI to GFX6-GFX7-GFX8Marek Olšák2019-05-155-24/+24
* v3d: Use driconf to expose non-MSAA texture limits for Xorg.Eric Anholt2019-05-136-15/+25
* winsys/amdgpu: add VCN JPEG to no user fence groupLeo Liu2019-05-101-1/+2
* virgl: export resource_is_busy from winsysChia-I Wu2019-05-062-11/+14
* svga: move host logging to winsysCharmaine Lee2019-05-025-0/+495
* winsys/svga: Don't abort on EBUSY errors from execbufferThomas Hellstrom2019-05-021-1/+3
* winsys/svga: Update the drm interface fileThomas Hellstrom2019-05-022-174/+188
* winsys/svga: Enable the transfer_from_buffer GPU command for vgpu10Thomas Hellstrom2019-05-021-0/+1
* winsys/svga: Add an environment variable to force host-backed operationThomas Hellstrom2019-05-021-6/+11
* winsys/svga/drm: Include sys/types.hKhem Raj2019-04-301-0/+1
* vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.Eric Anholt2019-04-262-3/+35
* kmsro: Add support for V3D.Eric Anholt2019-04-262-0/+16
* virgl/drm: insert correct handles into the table. (v3)Dave Airlie2019-04-251-1/+4
* virgl/drm: handle flink name better.Dave Airlie2019-04-252-20/+11
* virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2019-04-252-15/+13
* winsys/amdgpu: clean up and remove nonsensical assertionMarek Olšák2019-04-231-2/+1
* winsys/amdgpu: enable chaining for compute IBsMarek Olšák2019-04-231-6/+6
* winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE lastMarek Olšák2019-04-231-19/+17
* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-231-1/+3
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 16:55:19 +0000