| Commit message (Collapse) | Author | Age | Files | Lines |
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The combined VRAM|GTT heap will be removed.
Reviewed-by: Nicolai Hähnle <[email protected]>
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and handle PIPE_FLUSH_HINT_FINISH in r300.
Reviewed-by: Nicolai Hähnle <[email protected]>
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The next commit will reduce the size even more.
v2: typecast to uint64_t manually
v3: add more typecasts, add asserts
Reviewed-by: Nicolai Hähnle <[email protected]>
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Using build_by_default : false is convenient for dependencies that can
be pulled in by various diverse components of the build system, the
gallium hardware/software drivers and state trackers do not fit that
description. Instead, these should be guarded using the variable that tracks
whether that driver should be enabled.
This leaves a few helper libraries: trace, rbug, etc, and the generic
winsys bits as `build_by_default : false` because there are a large
number of gallium components that pull them in.
v2: - remove build_by_default from winsys convenience libs as well.
v3: - Always put drivers before winsys for consistency
Signed-off-by: Dylan Baker <[email protected]>
Tested-by: Lionel Landwerlin <[email protected]> (v1)
Reviewed-by: Eric Anholt <[email protected]>
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The idea is to fix the following interleaving of operations
that can arise from deferred fences:
Thread 1 / Context 1 Thread 2 / Context 2
-------------------- --------------------
f = deferred flush
<------- application-side synchronization ------->
fence_server_sync(f)
...
flush()
flush()
We will now stall in fence_server_sync until the flush of context 1
has completed.
This scenario was unlikely to occur previously, because applications
seem to be doing
Thread 1 / Context 1 Thread 2 / Context 2
-------------------- --------------------
f = glFenceSync()
glFlush()
<------- application-side synchronization ------->
glWaitSync(f)
... and indeed they probably *have* to use this ordering to avoid
deadlocks in the GLX model, where all GL operations conceptually
go through a single connection to the X server. However, it's less
clear whether applications have to do this with other WSI (i.e. EGL).
Besides, even this sequence of GL commands can be translated into
the Gallium-level sequence outlined above when Gallium threading
and asynchronous flushes are used. So it makes sense to be more
robust.
As a side effect, we no longer busy-wait on submission_in_progress.
We won't enable asynchronous flushes on radeon, but add a
cs_add_fence_dependency stub anyway to document the potential
issue.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
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It's inaccurate. Instead, see the copyright and use "git log" and
"git blame" to know the authorship.
Acked-by: Nicolai Hähnle <[email protected]>
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It shows the sum of all IBs per frame.
Reviewed-by: Nicolai Hähnle <[email protected]>
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This builds the radeonsi (and radeon) window system bits and gallium
driver bits.
Signed-off-by: Dylan Baker <[email protected]>
Reviewed-by: Eric Anholt <eric at anholt.net>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.
v2: It shouldn't crash anymore, but the kernel will reject the new flag.
v3 (christian): Rename the flag, avoid sending those buffers in the BO list.
v4 (christian): Remove setting the kernel flag for now
Reviewed-by: Marek Olšák <[email protected]>
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This allows a more generic mechanism for passing user configurations
into drivers by accessing the dri options directly.
Reviewed-by: Marek Olšák <[email protected]>
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It can't parse "llu".
Reviewed-by: Thomas Helland <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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This is cleaner, and we are down to 4 slabs.
Reviewed-by: Nicolai Hähnle <[email protected]>
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https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html
Reviewed-by: Nicolai Hähnle <[email protected]>
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I think it's unsafe, because the slabs can reuse exported storage.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100242
Fixes: fb827c055cb1 ("winsys/radeon: enable buffer allocation from slabs")
Cc: [email protected]
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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The CL CTS queries the max allocation size, and then attempts to
allocate buffers of that size. If not enough contiguous RAM/VRAM is
available, this causes errors in the radeon kernel module due to
inability to allocate the required memory.
It's a bit of a hack, but experimentally on my system, I can use ~3/4
of the card's VRAM for a single global/constant buffer allocation given
current GUI/compositor use.
For a 1GB Pitcairn (HD7850) this gets me from the reported clinfo values of:
Global memory size 2143076352 (1.996GiB)
Max memory allocation 1500153446 (1.397GiB)
Max constant buffer size 1500153446 (1.397GiB)
To:
Global memory size 2143076352 (1.996GiB)
Max memory allocation 751619276 (716MiB)
Max constant buffer size 751619276 (716MiB)
Fixes: OpenCL CTS test/conformance/api/min_max_mem_alloc_size,
OpenCL CTS test/conformance/api/min_max_constant_buffer_size
Signed-off-by: Aaron Watry <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
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Vulkan needs them.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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CID 1313492
Signed-off-by: Julien Isorce <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Like in a few other places in that radeon_drm_bo.c file.
CID 715739.
Signed-off-by: Julien Isorce <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Follow-up of patch:
"radeon_cs_create_fence: check null return from radeon_winsys_bo_create"
radeon_drm_cs_flush
radeon_cs_create_fence
radeon_winsys_bo_create
Signed-off-by: Julien Isorce <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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Fixes the following segmentation fault:
radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
-> if (!bo->handle)
(gdb) bt
0 radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
1 0x00007fffe73575de in radeon_cs_create_fence radeon_drm_cs.c
2 0x00007fffe7358c48 in radeon_drm_cs_flush radeon_drm_cs.c
Signed-off-by: Julien Isorce <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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pipe_mutex_unlock() was made unnecessary with fd33a6bcd7f12.
Replaced using:
find ./src -type f -exec sed -i -- \
's:pipe_mutex_unlock(\([^)]*\)):mtx_unlock(\&\1):g' {} \;
Reviewed-by: Marek Olšák <[email protected]>
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replace pipe_mutex_lock() was made unnecessary with fd33a6bcd7f12.
Replaced using:
find ./src -type f -exec sed -i -- \
's:pipe_mutex_lock(\([^)]*\)):mtx_lock(\&\1):g' {} \;
Reviewed-by: Marek Olšák <[email protected]>
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pipe_mutex_destroy() was made unnecessary with fd33a6bcd7f12.
Replace was done with:
find ./src -type f -exec sed -i -- \
's:pipe_mutex_destroy(\([^)]*\)):mtx_destroy(\&\1):g' {} \;
Reviewed-by: Marek Olšák <[email protected]>
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pipe_mutex_init() was made unnecessary with fd33a6bcd7f12.
Replace was done using:
find ./src -type f -exec sed -i -- \
's:pipe_mutex_init(\([^)]*\)):(void) mtx_init(\&\1, mtx_plain):g' {} \;
Reviewed-by: Marek Olšák <[email protected]>
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This was made unnecessary with fd33a6bcd7f12.
Reviewed-by: Marek Olšák <[email protected]>
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pipe_mutex was made unnecessary with fd33a6bcd7f12.
Reviewed-by: Marek Olšák <[email protected]>
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it's cleaner this way.
Reviewed-by: Nicolai Hähnle <[email protected]>
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This results in a very tiny decrease in lgkm wait cycles.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Provided by libdrm as of last commit.
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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The kernel driver reports correct values now.
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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the value from the kernel is wrong
Reviewed-by: Nicolai Hähnle <[email protected]>
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This just needs to be done for r600g in the screen.
We don't need an IB submission for every new context created for GCN.
Reviewed-by: Nicolai Hähnle <[email protected]>
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This new query returns the current visible usage of VRAM accessed
by the CPU. It will return 0 on radeon because it's unimplemented.
Signed-off-by: Samuel Pitoiset <[email protected]>
Tested-by: Edmondo Tommasina <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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