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* winsys/radeon: don't use BIND flags, add a flag for the cache bufmgr insteadMarek Olšák2012-12-122-5/+4
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* r300g: enable Hyper-Z by default on r500Marek Olšák2012-12-021-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | I fixed the only known bugs on r500 with 0222b2bd4107b9e5cabfbc06c1a6ca3eae. Now there are no piglit regressions with Hyper-Z and all apps I tested seem to work. To summarize how it works: - Only one process can use it at a time. This is a hardware limitation. - The first process to clear a zbuffer gets the exclusive access to use Hyper-Z. - Compositors don't use any zbuffer, so they won't steal it, but some web browsers do, so make sure there's no web browser running if you want your game to use Hyper-Z. - There's no need to restart an app which couldn't get the access to Hyper-Z. Just quit the app which took it, the driver can turn it on for the other app in the middle of rendering. - If an app gets the access to Hyper-Z, it prints "radeon: Acquired Hyper-Z" to stdout. r300-r400: Hyper-Z will be enabled by default on r300-r400 once sufficient testing is done with piglit and Lightsmark at least. Be sure to set the env var RADEON_HYPERZ and run piglit with parameters: -c 0
* winsys/radeon: fix relocs cachingVadim Girlin2012-09-192-8/+6
| | | | | | | | | | | Don't cache pointers to elements of reallocatable array. In some circumstances it caused false cache hits resulting in incorrect command stream and gpu lockup. Note: This is a candidate for the stable branches. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2012-09-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Don't cast the return value of malloc/realloc. // // Casting the return value of malloc/realloc only stands to hide // errors. @@ type T; expression E1, E2; @@ - (T) ( _mesa_align_calloc(E1, E2) | _mesa_align_malloc(E1, E2) | calloc(E1, E2) | malloc(E1) | realloc(E1, E2) )
* winsys/radeon: create only one winsys for each fdChristian König2012-09-042-2/+41
| | | | | | | Fixing problems with GLAMOR. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: Don't assign virtual address space for BO that already has one.Michel Dänzer2012-08-161-1/+1
| | | | | | | | We'd end up re-using the old one and throwing away the new one anyway, but only after a roundtrip to the kernel. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Create hole for waste when allocating from va_offset.Michel Dänzer2012-08-161-0/+6
| | | | | | | Otherwise, the wasted area could never be used for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Fix potential address space loss in radeon_bomgr_force_va().Michel Dänzer2012-08-161-6/+13
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Delete uppermost virtual address space hole if it's at the top.Michel Dänzer2012-08-161-1/+12
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Fix losing holes when allocating virtual address space.Michel Dänzer2012-08-161-1/+6
| | | | | | | | | If a hole exactly matches the allocated size plus alignment, we would fail to preserve the alignment as a hole. This would result in never being able to use the alignment area for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Merge holes when freeing virtual address space.Michel Dänzer2012-08-161-7/+38
| | | | | | | | | | Otherwise we'll likely end up with an ever increasing amount of ever smaller holes. Requires keeping the list ordered wrt offsets. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Make va_offset 64 bits wide.Michel Dänzer2012-08-161-1/+1
| | | | | | | | | | Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU virtual address space to 4GB anyway, but that will probably change sooner or later, and this would result in confusing error messages when running out of virtual address space even now. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement timestamp query and get_timestamp hookMarek Olšák2012-08-152-0/+28
| | | | Reviewed-by: Alex Deucher <[email protected]>
* configure.ac: bump libdrm_radeon requirement to 2.6.38Marek Olšák2012-08-151-1/+0
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* winsys/radeon: print error if CS is overflowedMarek Olšák2012-08-151-2/+6
| | | | and don't submit the CS to the kernel.
* radeon/winsys: fix winsys VM handlingChristian König2012-08-081-3/+4
| | | | | | | | | Move releasing the VM area after closing the bo handle. This partially fixes: https://bugs.freedesktop.org/show_bug.cgi?id=45018 Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable streamout by default on r7xx and DRM 2.17.0Marek Olšák2012-06-172-3/+0
| | | | | | Now that it's in Linus's tree. Has anyone had a chance to test streamout on Cayman recently?
* winsys/radeon: enable IB submission to compute rings v2Christian König2012-06-153-7/+15
| | | | | | | | | | | This allows to submit things to the compute only rings on cayman+ v2: rebased on current master and actually make use of the new flag in evergreen_compute.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: Remove unnecessary pipe_thread_destroy in radeon_drm_cs_destroyMaarten Lankhorst2012-06-151-1/+0
| | | | | | | | Fixes crash bug introduced with 210ddf0819b5 fd.o #49198 pthread_detach after a pthread_join is unneeded. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon: Fix r300g tiling breakage.Michel Dänzer2012-05-162-3/+14
| | | | | | Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it up, and reinstate some code which isn't needed by r600g and radeonsi but is by r300g.
* radeonsi: Initial tiling support.Michel Dänzer2012-05-161-2/+2
| | | | Largely based on the corresponding Evergreen support in r600g.
* r600g: Set tiling information for BOs being shared.Michel Dänzer2012-05-162-9/+35
| | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=48747
* winsys/radeon: Get max_pipes from the kernelTom Stellard2012-05-022-0/+11
| | | | Signed-off-by: Tom Stellard <[email protected]>
* winsys/radeon: simplify buffer map/unmap functionsMarek Olšák2012-04-292-40/+16
| | | | | The idea is not to use pb_map and pb_unmap wrappers, calling straight into the winsys.
* radeonsi: initial WIP SI codeTom Stellard2012-04-132-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <[email protected]> Michel Dänzer <[email protected]> Alex Deucher <[email protected]> Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <[email protected]> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <[email protected]> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <[email protected]> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <[email protected]> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <[email protected]> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
* r600g: optimize r600_resource_vaMarek Olšák2012-04-012-5/+3
| | | | Avoid calling get_radeon_bo and inline it.
* r600g: enable transform feedback on everything that isn't r700Marek Olšák2012-03-271-2/+1
| | | | Use R700_STREAMOUT=1 if you wanna hack transform feedback on r700.
* winsys/radeon: cleanup includesMarek Olšák2012-03-051-3/+1
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* winsys/radeon: add usage parameter to cs_is_buffer_referencedMarek Olšák2012-03-052-3/+18
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: check for R600_STREAMOUT env var in winsysMarek Olšák2012-02-272-0/+5
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* radeon/r600g: fix virtual address space allocationJerome Glisse2012-02-211-0/+3
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix tiling with cayman and virtual memoryJerome Glisse2012-02-141-10/+28
| | | | | | | | | The virtual address but follow the alignment requirement of the tiled surface. The bo from handle case is not properly fix. Need bigger change for a proper fix. Work around that by enforcing 1M alignment for those bo. Signed-off-by: Jerome Glisse <[email protected]>
* radeon: only init surface manage on r600Dave Airlie2012-02-071-4/+8
| | | | | | r300 fails to init the manager and then fails to init. Signed-off-by: Dave Airlie <[email protected]>
* scons: r300/r600 now depends on libdrm.José Fonseca2012-02-071-1/+1
| | | | As they now indirectly include on libdrm/radeon_surface.h.
* r600g: add support for common surface allocator for tiling v13Jerome Glisse2012-02-064-2/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]>
* r600g: remove unused flush codeMarek Olšák2012-01-312-13/+1
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* r600g: add support for virtual address space on cayman v11Jerome Glisse2012-01-136-10/+273
| | | | | | | | | | | | | | | | | | | | | | | | | Virtual address space put the userspace in charge of their GPU address space. It's up to userspace to bind bo into the virtual address space. Command stream can them be executed using the IB_VM chunck. This patch add support for this configuration. It doesn't remove the 64K ib size limit thought this limit can be extanded up to 1M for IB_VM chunk. v2: fix rendering v3: fix rendering when using index buffer v4: make vm conditional on kernel support add basic va management v5: catch the case when we already have va for a bo v6: agd5f: update on top of ioctl changes v7: agd5f: further ioctl updates v8: indentation cleanup + fix non cayman v9: rebase against lastest mesa + improvement from Marek & Michel v10: fix cut/paste bug v11: don't rely on updated radeon_drm.h Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeon/winsys: fix get info ioctl error checkingJerome Glisse2012-01-091-3/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* winsys/radeon: move managing GEM domains back to driversMarek Olšák2011-12-244-56/+40
| | | | | | | | This partially reverts commit 363ff844753c46ac9c13866627e096b091ea81f8. It caused severe performance drops in Nexuiz. Reported by Phoronix. Tested by me on r300g and by IRC people on r600g.
* winsys/radeon: add flush option not to rewrite tiling flags in registersMarek Olšák2011-12-133-4/+24
| | | | Not used yet.
* gallium/radeon: fix indentationJerome Glisse2011-12-054-28/+28
| | | | | | Indentation cleanup, to keep consistency. Signed-off-by: Jerome Glisse <[email protected]>
* radeon: silence initializer warningsBrian Paul2011-11-102-11/+33
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* winsys/radeon: don't use the new GEM_WAIT ioctl for nowMarek Olšák2011-10-241-4/+6
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* winsys/radeon: restore the old r600g winsys memory characteristics.Mathias Fröhlich2011-10-241-0/+5
| | | | | | | | | Use VRAM for static and immutable buffers. This restores the recently removed r600g winsys behaviour for memory locations. This also improoves rendering times on the gpu for some OpenSceneGraph based test cases by about 15%. Signed-off-by: Marek Olšák <[email protected]>
* configure: replace pkg-config calls with $(PKG_CONFIG) in the makefiles.Stéphane Marchesin2011-10-041-1/+1
| | | | | | | Us poor souls who cross compile mesa want to be able to specify which pkg-config to pick, or at least just change one place. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* winsys/radeon: move GEM domains out of the drivers into winsysMarek Olšák2011-09-304-40/+58
| | | | | | | | | | | | | | | The drivers don't need to care about the domains. All they need to set are the bind and usage flags. This simplifies the winsys too. This also fixes on r600g: - fbo-depth-GL_DEPTH_COMPONENT32F-copypixels - fbo-depth-GL_DEPTH_COMPONENT16-copypixels - fbo-depth-GL_DEPTH_COMPONENT24-copypixels - fbo-depth-GL_DEPTH_COMPONENT32-copypixels - fbo-depth-GL_DEPTH24_STENCIL8-copypixels I can't explain it. Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: remove a redundant parameter 'size' from buffer_from_handleMarek Olšák2011-09-302-8/+3
| | | | | | It's part of pb_buffer already. Reviewed-by: Alex Deucher <[email protected]>
* r600g: merge r600_bo with r600_resourceMarek Olšák2011-09-302-1/+13
| | | | | | | I have moved 'last_flush' and 'binding' from r600_bo to winsys/radeon. The other members are now part of r600_resource. Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: remove redundant member radeon_bo::sizeMarek Olšák2011-09-293-8/+5
| | | | It's part of pb_buffer already.
* winsys/radeon: simplify updating GEM domains for relocationsMarek Olšák2011-09-291-10/+2
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