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* r300g: restore performance after RADEON_FLAG_NO_INTERPROCESS_SHARING was addedRichard Thier2019-06-141-1/+3
| | | | | | | | | | | | | | | | v1: Fix skipped slab allocators and the buffer cache. v2: Use only 1 domain for texture allocation v3: Added flag for the create_fence call too Based on Marek v1 and v2 proposed fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=1107812.patch Cc: 19.1 <[email protected]> Signed-off-by: Marek Olšák <[email protected]> (cherry picked from commit ffd2f948fee271cbbce93708fc508dab7cb5d14c)
* Delete autotoolsDylan Baker2019-04-151-12/+0
| | | | | | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Matt Turner <[email protected]>
* winsys/amdgpu,radeon: pass vm_alignment to buffer_from_handleMarek Olšák2018-11-282-1/+3
| | | | Acked-by: Christian König <[email protected]>
* radeonsi: stop command submission with PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET onlyMarek Olšák2018-11-091-1/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: adjust and simplify max_alloc_size determinationMarek Olšák2018-09-101-3/+5
| | | | Tested-by: Dieter Nützel <[email protected]>
* ac: add radeon_info::num_good_cu_per_shMarek Olšák2018-09-101-0/+4
| | | | Tested-by: Dieter Nützel <[email protected]>
* winsys/radeon: fix CMASK fast clear for NPOT textures with mipmapping on SI/CIMarek Olšák2018-09-101-2/+2
| | | | | Cc: 18.2 <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: pin the winsys thread to the requested L3 cache (v2)Marek Olšák2018-09-071-0/+13
| | | | | | v2: rebase Reviewed-by: Brian Paul <[email protected]>
* ac: add radeon_info::nameMarek Olšák2018-08-141-1/+6
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: use storage_samples instead of color_samples in most placesMarek Olšák2018-07-311-4/+2
| | | | | | | and use pipe_resource::nr_storage_samples instead of r600_texture::num_color_samples. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: rework RADEON_PRIO flags to be <= 31Marek Olšák2018-07-162-2/+2
| | | | | | This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes. Reviewed-by: Samuel Pitoiset <[email protected]>
* Shorten u_queue namesMarek Olšák2018-07-041-1/+1
| | | | | | | | There is a 15-character limit for thread names shared by the queue name and process name. Shorten the thread name to make space for the process name. Reviewed-by: Timothy Arceri <[email protected]>
* radeon: duplicate cmask surface for now.Dave Airlie2018-06-261-1/+61
| | | | | | | | The radeon winsys isn't linked against the ac code, I have vague memories of this causing some problems before, for now fix the build but just duplicating the code. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move CMASK size computation into ac_surfaceMarek Olšák2018-06-251-0/+13
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-194-19/+19
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac/gpu_info: add radeon_info::num_tcc_blocksMarek Olšák2018-06-191-0/+26
| | | | | | The values for the radeon winsys were copied from the kernel driver. Tested-by: Dieter Nützel <[email protected]>
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-301-7/+7
| | | | | | | | | | | | This just renames this as we want to add an shm handle which isn't really drm related. Originally by: Marc-André Lureau <[email protected]> (airlied: I used this sed script instead) This was generated with: git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g' Reviewed-by: Marek Olšák <[email protected]>
* ac/gpu_info: add has_read_registers_queryMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_2d_tilingMarek Olšák2018-05-101-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_sparse_vm_mappingsMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_unaligned_shader_loadsMarek Olšák2018-05-101-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_indirect_compute_dispatchMarek Olšák2018-05-101-0/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add kernel_flushes_tc_l2_after_ibMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_format_bc1_through_bc7Marek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_eqaa_surface_allocatorMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up the reset status query implementationMarek Olšák2018-05-101-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_bo_metadataMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowedMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add htile_cmask_support_1d_tilingMarek Olšák2018-05-101-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add kernel_flushes_hdp_before_ibMarek Olšák2018-05-101-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add EQAA supportMarek Olšák2018-05-101-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: unify common legacy and gfx9 fmask fieldsMarek Olšák2018-05-101-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface/gfx6: compute FMASK together with the color surfaceMarek Olšák2018-05-101-0/+48
| | | | | | instead of invoking FMASK computation separately. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: Destroy fd_hash table when the last winsys is removed.Jan Vesely2018-05-101-1/+6
| | | | | | | | | Fixes memory leak on module unload. v2: Use util_hash_table helper function CC: <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Jan Vesely <[email protected]>
* radeonsi: don't emit partial flushes for internal CS flushes onlyMarek Olšák2018-04-162-5/+10
| | | | | Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: rename has_virtual_memory -> r600_has_virtual_memoryMarek Olšák2018-04-023-17/+17
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* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-081-0/+1
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: implement and enable 32-bit VM allocationsMarek Olšák2018-02-173-8/+64
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/radeon: add struct radeon_vm_heapMarek Olšák2018-02-173-36/+47
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/radeon: Compute is_displayable in surf_drm_to_winsysMichel Dänzer2018-01-311-0/+3
| | | | | | | | It was always 0, breaking (at least) DRI3 with Xwayland. Bugzilla: https://bugs.freedesktop.org/104306 Fixes: 5f2073be3282 ("ac/surface: add ac_surface::is_displayable") Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: set number of pb_cache buckets = number of heapsMarek Olšák2018-01-272-16/+13
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* pb_cache: let drivers choose the number of bucketsMarek Olšák2018-01-272-2/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* autotools: include meson build files in tarballDylan Baker2018-01-191-0/+2
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/radeon: fix up default enabled_rb_mask for r600Roland Scheidegger2018-01-101-6/+10
| | | | | | | | | | | | | | The logic had two fatal flaws which completely killed the default value. 1) drm will overwrite the value anyway even if the chip can't be handled 2) the default value logic is relying on num_render_backends, which was filled in later. Luckily noone is relying on it, but it's a bit confusing seeing the chip clock printed out there (as hex) with R600_DEBUG=info... (Albeit radeonsi does not appear to fix up the value. If kernels which don't handle this query are still supported, radeonsi will still end up with a broken enabled_rb_mask, I have no idea of the potential results of this there.) Reviewed-by: Dave Airlie <[email protected]>
* gallium/radeon: move setting VRAM|GTT into winsysesMarek Olšák2017-12-052-0/+15
| | | | | | The combined VRAM|GTT heap will be removed. Reviewed-by: Nicolai Hähnle <[email protected]>
* r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*Marek Olšák2017-11-292-5/+5
| | | | | | and handle PIPE_FLUSH_HINT_FINISH in r300. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: change legacy_surf_level::slice_size to dword unitsMarek Olšák2017-11-271-2/+2
| | | | | | | | | The next commit will reduce the size even more. v2: typecast to uint64_t manually v3: add more typecasts, add asserts Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-131-1/+0
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fencesNicolai Hähnle2017-11-091-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to fix the following interleaving of operations that can arise from deferred fences: Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = deferred flush <------- application-side synchronization -------> fence_server_sync(f) ... flush() flush() We will now stall in fence_server_sync until the flush of context 1 has completed. This scenario was unlikely to occur previously, because applications seem to be doing Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = glFenceSync() glFlush() <------- application-side synchronization -------> glWaitSync(f) ... and indeed they probably *have* to use this ordering to avoid deadlocks in the GLX model, where all GL operations conceptually go through a single connection to the X server. However, it's less clear whether applications have to do this with other WSI (i.e. EGL). Besides, even this sequence of GL commands can be translated into the Gallium-level sequence outlined above when Gallium threading and asynchronous flushes are used. So it makes sense to be more robust. As a side effect, we no longer busy-wait on submission_in_progress. We won't enable asynchronous flushes on radeon, but add a cs_add_fence_dependency stub anyway to document the potential issue. Reviewed-by: Marek Olšák <[email protected]>
* util: move os_time.[ch] to src/utilNicolai Hähnle2017-11-092-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
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