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* r600g: don't emit color blend register on original R600.Dave Airlie2011-05-312-8/+15
| | | | | | The original R600 doesn't have these so don't emit them. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add initial cayman acceleration support.Dave Airlie2011-05-253-4/+424
| | | | | | | | | | | | | | | | Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <[email protected]>
* r600g: flush the DB dest base as well.Dave Airlie2011-05-251-1/+1
| | | | | | | | If we do this for CB bases then we should do it for DB bases. noticed while adding cayman support. Signed-off-by: Dave Airlie <[email protected]>
* r600g: bump domain selection up one layer.Dave Airlie2011-05-183-6/+24
| | | | | | | this is taken from a patch from Mathias Froehlich, just going to stage it in a few pieces. Signed-off-by: Dave Airlie <[email protected]>
* r600g: reduce flushes so only when texture and CB overlap.Dave Airlie2011-05-152-8/+17
| | | | | | | We only need to do this when the texture and CB are using the same memory area. Signed-off-by: Dave Airlie <[email protected]>
* r600g: don't unmap if we haven't mappedDave Airlie2011-05-131-2/+4
| | | | | | should fix https://bugs.freedesktop.org/show_bug.cgi?id=37157 Signed-off-by: Dave Airlie <[email protected]>
* r600g: use a local var to store pointer to which register we are working onDave Airlie2011-05-131-7/+8
| | | | | | this just makes the code a little bit cleaner. Signed-off-by: Dave Airlie <[email protected]>
* r600g: make range/block act more like a page tableDave Airlie2011-05-133-50/+45
| | | | | | | | | | | | | | | | only allocate the blocks ptr in the range if we ever have one, otherwise don't bother wasting the memory. valgrind glxinfo before: ==967== in use at exit: 419,754 bytes in 706 blocks ==967== total heap usage: 3,552 allocs, 2,846 frees, 3,550,131 bytes allocated after: ==5227== in use at exit: 419,754 bytes in 706 blocks ==5227== total heap usage: 3,452 allocs, 2,746 frees, 3,140,531 bytes allocate Signed-off-by: Dave Airlie <[email protected]>
* r600g: reduce r600_reg footprintDave Airlie2011-05-133-788/+785
| | | | | | | | This drops 6k of the text segment, a minor drop in the ocean, however it also makes the code a lot cleaner and removes a lot of duplicated information, hopefully making it more maintainable. Signed-off-by: Dave Airlie <[email protected]>
* r600g: reduce memory usage from range/block hash table.Dave Airlie2011-05-133-23/+38
| | | | | | | | | | | | | | | | | | This table covered a large range unnecessarily, reduce the address range covered, use the fact that the bottom two bits aren't significant, and remove unused fields from the range struct. It also drops the hash_size/shift in context in favour of a define, which should make doing the math a bit less CPU intensive. valgrind glxinfo Before: ==320== in use at exit: 419,754 bytes in 706 blocks ==320== total heap usage: 3,691 allocs, 2,985 frees, 7,272,467 bytes allocated After: ==967== in use at exit: 419,754 bytes in 706 blocks ==967== total heap usage: 3,552 allocs, 2,846 frees, 3,550,131 bytes allocated Signed-off-by: Dave Airlie <[email protected]>
* r600g: delay mapping until first map request. (v2)Dave Airlie2011-05-132-6/+4
| | | | | | | | | | | | | | Currently r600g always maps every bo, this is quite pointless as it wastes VM and on 32-bit with wine running VM space is quite useful. So with this patch we don't create the mappings until first use, without tiling enabled this probably won't make a major difference on its own, but with tiled staged uploads it should avoid keeping maps for most of the textures unnecessarily. v2: add bo data ptr check Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix flushes on rs780/rs880Alex Deucher2011-05-111-1/+3
| | | | | | | | | They need the same hack as rv670. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35312 Signed-off-by: Alex Deucher <[email protected]>
* r600g: avoid recursion in rv670 flush workaroundAlex Deucher2011-05-061-2/+7
| | | | | | | Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=36914 Signed-off-by: Alex Deucher <[email protected]>
* Add pci id for FirePro 2270Kostas Georgiou2011-05-061-0/+1
| | | | Signed-off-by: Kostas Georgiou <[email protected]>
* r600g: further r6xx cache flush fixesAlex Deucher2011-05-051-12/+10
| | | | | | | Don't emit sync packets for additional CBs or DB. Spotted by Fredrik Höglund. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add rv670 flushing workaround.Dave Airlie2011-05-061-0/+4
| | | | | | | Hopefully we can find out the proper fix for this, but for now this makes the fbo mipmap tests pass on my rv670 (x2 card). Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix cache flushes on r6xxAlex Deucher2011-05-061-9/+27
| | | | | | | | | | | | | | | r6xx asics have some problems with the surface sync logic for the CB and DB. It's recommended to use the event write interface for flushing the DB/CB caches rather than the sync packets. A single event write flush flushes all dst caches, so we only need one for all CBs and DB. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=35312 Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: do RV6xx base updates inline with state updates.Dave Airlie2011-05-052-54/+22
| | | | | | | | | This seems more in line with what the documentation suggests we should be doing. It doesn't fix the rv635 regression, though I thought it might, so it means I've no idea whats actually going wrong there. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add some new pci idsAlex Deucher2011-05-031-0/+4
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: remove some pointless and unused functionsMarek Olšák2011-04-253-21/+3
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* r600g: do not reset device to 0 when doing unrelated operationsMarek Olšák2011-04-251-2/+0
| | | | Seems to be a copy-paste bug.
* r600g: fix userspace fences againAlex Deucher2011-04-201-0/+3
| | | | | | | reinstate b7617346dcff50a66a10c61b95c33682cf629c9e after the rework in 6067a2a67f9a7aab2aee051469bea8af03747a95. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't flush the dest caches on every drawFredrik Höglund2011-04-202-67/+141
| | | | | | | Keep track of when the caches are dirty, and only flush them when the framebuffer state is set and when the context is flushed. Signed-off-by: Dave Airlie <[email protected]>
* r600g: make loop const always flushDave Airlie2011-04-192-2/+2
| | | | | | | | this needs revisiting, we really don't want to be flushing all 32 of these, but currently we don't flush any of them, and it seems to have caused a regression as reported on irc with doom3 on evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add dirty tracking to context reg.Dave Airlie2011-04-191-7/+12
| | | | | | just makes the code more consistent. Signed-off-by: Dave Airlie <[email protected]>
* r600g: deinline some large functions.Dave Airlie2011-04-192-76/+83
| | | | | | really at these sort of sizes these are pointless inlines. Signed-off-by: Dave Airlie <[email protected]>
* r600g: consolidate r600/evergreen code for resource emission.Dave Airlie2011-04-193-41/+8
| | | | | | These really didn't have much difference, and totally not inline material. Signed-off-by: Dave Airlie <[email protected]>
* r600g: don't flush caches if we already did so, even for a subset of the flagsBas Nieuwenhuizen2011-04-191-2/+2
| | | | | | | Merging the flushes that are left doesn't seem to give a significant performance improvement Signed-off-by: Dave Airlie <[email protected]>
* r600g: attempt to avoid emitting resources that are the sameDave Airlie2011-04-191-18/+49
| | | | | | This just avoids reemitting resources that haven't changed. Signed-off-by: Dave Airlie <[email protected]>
* r600g: modify block to only emit the first few dirty registers. (v2)Dave Airlie2011-04-193-11/+37
| | | | | | | | | | | This gets me from 2200 to 1978 dwords for a gears frame. This is due to us having some 32-dwords blocks in the SPI, that we only modify the first dwords off. v2: fix dirty reg count from Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* r600g: track dirty registers better. (v2)Dave Airlie2011-04-193-121/+170
| | | | | | | | | | | | | | | | | | | | | | | | | This is a first step to decreasing the CPU usage, by decreasing how much stuff we pass to the GPU and hence to the kernel CS checker. This adds a check to see if the values we need to write are actually dirty, and avoids writing if they are. However certain register need to always be written so we add a new flag to say which ones should be always written if used. (Note this could probably be done cleaner with a larger refactoring, since I think the CONST_BUFFER_SIZE_PS/VS and CONST_CACHE_PS/VS might be better off as a special state). It also moves the need_bo to be a flags on the register now. With this, a frame of gears goes from emitting 3k dwords to emitting 2k dwords, and I'm sure it could get a lot smaller. v2: fix some evergreen dirty bits. Original patch from: Bas Nieuwenhuizen, I NIHed nearly the same thing before seeing his patch on the list, oops. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* r600g: use some loops.Dave Airlie2011-04-172-29/+24
| | | | | | | unrolling loops is for Gentoo users, and I really want to put something else inside these loops later. Signed-off-by: Dave Airlie <[email protected]>
* r600g: consolidate the same piece of cut-n-paste code into a function.Dave Airlie2011-04-173-42/+21
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: add some additional ontario pci idsAlex Deucher2011-04-041-0/+2
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: implement texture barrierFredrik Höglund2011-03-291-0/+17
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* r600g: implement the pipe_screen fence functionsFredrik Höglund2011-03-291-0/+23
| | | | | | v2: Allocate the fences from a single shared buffer object. v3: Allocate the r600_fence structs in blocks of 16. Spin a few times before calling sched_yield in r600_fence_finish().
* r600g: fix bo names causing -35 EDEADLCKDave Airlie2011-03-223-0/+48
| | | | this is a port of the r300 winsys code to do the same thing.
* r600g: fix logic error in 028987c80362eddd39176628486a456b076f0427Alex Deucher2011-03-141-1/+1
| | | | | | Spotted by Henri on IRC. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit SURFACE_BASE_UPDATE packet on rv6xxAlex Deucher2011-03-142-2/+25
| | | | | | | | This packet is required when updating the DB, CB, or STRMOUT base addresses on rv6xx for the surface sync logic to work correctly. Signed-off-by: Alex Deucher <[email protected]>
* gallium: remove flags from the flush functionMarek Olšák2011-03-111-1/+1
| | | | | | | | | | The drivers have been changed so that they behave as if all of the flags were set. This is already implicit in most hardware drivers and required for multiple contexts. Some state trackers were also abusing the PIPE_FLUSH_RENDER_CACHE flag to decide whether flush_frontbuffer should be called. New flag ST_FLUSH_FRONT has been added to st_api.h as a replacement.
* r600: don't close fd on failed loadDave Airlie2011-03-101-3/+0
| | | | | | | This fd gets passed in from outside, closing it causes the X.org server to crap out when the driver doesn't identify the chipset. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add NV_conditional_render support.Dave Airlie2011-03-013-26/+80
| | | | | | | | This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <[email protected]>
* r600g: start using drm minor version to enable things.Dave Airlie2011-03-012-6/+61
| | | | | | | | | | If the drm minor version is > 9 (i.e. whats in drm-next), we enable s3tc + texture tiling by default now. this changes R600_FORCE_TILING to R600_TILING which can be set to false to disable tiling on working drm. Signed-off-by: Dave Airlie <[email protected]>
* r600g: silence a few valgrind warningsBrian Paterni2011-02-083-4/+4
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* r600g: Make some more things static.Henri Verbeet2011-02-031-1/+1
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* r600g: align the tiling modes with what the DDX and kernel expects.Dave Airlie2011-02-011-4/+3
| | | | | | | If we see a MACRO bit on r600g its 2D tiled, if don't see a MACRO bit and we do see a MICRO bit then its 1D tiled. Signed-off-by: Dave Airlie <[email protected]>
* r600g: start looking at evergreen tiling.Dave Airlie2011-02-011-17/+60
| | | | | | | | this just adds the ioctl interface and sets the tile type and array mode in the correct place. This seems to bring eg 1D tiling to the same level, and issues as on r600. No idea how to address 2D yet.
* scons: Gracefully handle pkg-config errors with libdrm_radeon.Vinson Lee2011-01-311-1/+6
| | | | Print warnings and continue build.
* r600g: fix eg OQ properly.Dave Airlie2011-01-312-5/+3
| | | | the context init is separate for these gpus.
* r600g: fix OQ on evergreenAlex Deucher2011-01-311-3/+6
| | | | | | 6xx/7xx have a max of 4 DBs, evergreen have a max of 8. Signed-off-by: Alex Deucher <[email protected]>
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