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* winsys/amdgpu: use only one fence per BONicolai Hähnle2016-09-123-68/+56
| | | | | | | | | | | The fence that is added to the BO during flush is guaranteed to be signaled after all the fences that were in the fences array of the BO before the flush, because those fences are added as dependencies for the submission (and all this happens atomically under the bo_fence_lock). Therefore, keeping only the last fence around is sufficient. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add do_winsys_deinit functionNicolai Hähnle2016-09-121-2/+7
| | | | | | | The idea is to have matching init/deinit functions so that deinit can be re-used for cleanup in the error path of amdgpu_winsys_create. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: clean up error paths in amdgpu_winsys_createNicolai Hähnle2016-09-121-7/+5
| | | | | | | No need to call pb_cache_deinit, because the cache hasn't been initialized at that point. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon/winsyses: remove #includes of pb_bufmgr.hNicolai Hähnle2016-09-121-1/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: replace OUT_CS with radeon_emitMarek Olšák2016-09-091-14/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: fix counting mapped memoryMarek Olšák2016-09-071-0/+8
| | | | | | Not all buffers are unmapped explicitly. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-0623-21944/+3
| | | | | Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move sid.h/r600d_common.h to a common place.Dave Airlie2016-09-061-1/+1
| | | | | | | | | | Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: disable IB chaining on SIMarek Olšák2016-08-261-5/+6
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: finish up SI addrlib integrationMarek Olšák2016-08-261-5/+25
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* winsys/amdgpu: initial SI supportRonie Salgado2016-08-263-6/+46
| | | | | Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: add a driver query for AMDGPU_INFO_NUM_EVICTIONSMarek Olšák2016-08-261-0/+7
| | | | | | If the kernel driver doesn't support it, it returns 0. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: track the amount of mapped memoryMarek Olšák2016-08-104-1/+24
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: don't try to unmap userptr buffersMarek Olšák2016-08-101-0/+3
| | | | | | no app calls this AFAIK Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: query ME/PFP/CE firmware versionsNicolai Hähnle2016-08-081-0/+22
| | | | | | | The radeon kernel module doesn't have the firmware query interface, so the corresponding values will remain 0. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: implement cs_get_next_fenceMarek Olšák2016-08-062-4/+35
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move radeon_winsys::cs_memory_below_limit to driversMarek Olšák2016-08-061-18/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: inline radeon_winsys::query_memory_usageMarek Olšák2016-08-061-6/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: expose per-IB used_vram and used_gart to driversMarek Olšák2016-08-062-11/+8
| | | | | | The following patches will use this. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: print CS submission error numberMarek Olšák2016-08-061-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: use pb_cache buckets for fewer pb_cache missesMarek Olšák2016-07-191-6/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/pb_cache: divide the cache into buckets for reducing cache missesMarek Olšák2016-07-191-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_queue: add optional cleanup callbackRob Clark2016-07-161-1/+1
| | | | | | | | | | | | Adds a second optional cleanup callback, called after the fence is signaled. This is needed if, for example, the queue has the last reference to the object that embeds the util_queue_fence. In this case we cannot drop the ref in the main callback, since that would result in the fence being destroyed before it is signaled. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: return an error on IB submission failuresMarek Olšák2016-07-142-1/+9
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/radeon: add a return value to cs_flushMarek Olšák2016-07-141-3/+4
| | | | | | Required by our UVD code. Reviewed-by: Christian König <[email protected]>
* radeonsi: just save buffer sizes instead of buffers while recording IBsMarek Olšák2016-07-131-1/+1
| | | | | | whole buffer objects are not needed Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: avoid flushed depth when possibleNicolai Hähnle2016-07-061-3/+8
| | | | | | | If a depth/stencil texture has no mipmaps, we can always get a layout that is compatible with DB and TC. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add depth/stencil_adjusted output to surface computationNicolai Hähnle2016-07-061-0/+4
| | | | | | | | | | | This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga, though it's basically a function of the memory configuration so could affect other parts as well. Fixes piglit "unaligned-blit * stencil downsample" and various "fbo-depth-array *stencil*" tests. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon/winsyses: remove unused stencil_offsetNicolai Hähnle2016-07-061-2/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add and use radeon_info::max_alloc_size (v2)Marek Olšák2016-07-051-0/+2
| | | | | | | | | | v2: - squashed the patches - use INT_MAX - clamp max_const_buffer_size - check the DRM version in radeon Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Vedran Miletić <[email protected]>
* radeon uvd add uvd fw version for amdgpusonjiang2016-06-291-1/+10
| | | | | | | Signed-off-by: sonjiang <[email protected]> Cc: "12.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: always calculate DCC info even if it's not used immediatelyMarek Olšák2016-06-291-1/+0
| | | | | | for a later use Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-254-37/+38
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabledNicolai Hähnle2016-06-243-2/+8
| | | | | | This should help flush out GPU VM faults. Reviewed-by: Marek Olšák <[email protected]>
* gallium/u_queue: allow the execute function to differ per jobMarek Olšák2016-06-242-2/+3
| | | | | | so that independent types of jobs can use the same queue. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_queue: add an option to name threadsMarek Olšák2016-06-241-1/+1
| | | | | | | | for debugging v2: correct the snprintf use Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_queue: add an option to have multiple worker threadsMarek Olšák2016-06-243-4/+4
| | | | | | | | independent jobs don't have to be stuck on only one thread v2: use CALLOC & FREE Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_queue: use a ring instead of a stackMarek Olšák2016-06-241-1/+1
| | | | | | | | and allow specifying its size in util_queue_init. v2: use CALLOC & FREE Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: import the multithreaded job queue from amdgpu winsys (v2)Marek Olšák2016-06-154-83/+18
| | | | | | v2: rename the event to util_queue_fence Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add micro_tile_mode to radeon_surfMarek Olšák2016-06-141-0/+15
| | | | | | for easier access Reviewed-by: Nicolai Hähnle <[email protected]>
* Android: move libdrm settings to top-level Android.common.mkRob Herring2016-06-131-1/+1
| | | | | | | | | | | | | | Fix warnings like these due to HAVE_LIBDRM being inconsistently defined: external/libdrm/include/drm/drm.h:839:30: warning: redefinition of typedef 'drm_clip_rect_t' is a C11 feature [-Wtypedef-redefinition] typedef struct drm_clip_rect drm_clip_rect_t; HAVE_LIBDRM needs to be set project wide to fix this. This change also harmlessly links libdrm with everything, but simplifies the makefiles a bit. Signed-off-by: Rob Herring <[email protected]> Acked-by: Emil Velikov <[email protected]>
* winsys/amdgpu: enable DCC for mipmapped texturesMarek Olšák2016-06-081-6/+23
| | | | | | | | Also add dcc_fast_clear_size for clearing only the necessary subset of DCC. For no AA, it's equal to the size of the whole DCC level. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add per-level dcc_enabled flagsMarek Olšák2016-06-081-3/+7
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: don't allocate DCC for non-renderable texture formatsMarek Olšák2016-06-081-0/+1
| | | | | | | | | | | R9G9B9E5 is the only uncompressed one hopefully. This fixes incorrect rendering not discovered (due to a lack of tests) until DCC mipmapping was enabled. Cc: 11.1 11.2 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: decay max_ib_size over timeNicolai Hähnle2016-06-011-0/+2
| | | | | | So that memory use will eventually decrease again after a temporary peak. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: implement IB chaining on the gfx ringNicolai Hähnle2016-06-012-18/+109
| | | | | | As a consequence, CE IB size never triggers a flush anymore. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: consolidate IB size management in amdgpu_ib_finalizeNicolai Hähnle2016-06-011-9/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/winsys: introduce radeon_winsys_cs_chunkNicolai Hähnle2016-06-011-24/+29
| | | | | | | We will chain multiple chunks together and will keep pointers to the older chunks to support IB dumping. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: start with smaller IBs, growing as necessaryNicolai Hähnle2016-06-012-10/+71
| | | | | | | | | | | | | | | | | This avoids allocating giant IBs from the outset, especially for CE and DMA. Since we now limit max_dw only by the size that the buffer happens to be (which, due to the buffer cache, can be even larger than the rounded-up size we request), the new function amdgpu_ib_max_submit_dwords controls when we submit an IB. With this change, we effectively never flush prematurely due to the CE IB, after an initial warm-up phase. v2: - clean up buffer_size calculation Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add amdgpu_ib and amdgpu_cs_from_ib helper functionsNicolai Hähnle2016-06-012-7/+37
| | | | | | | The latter function allows getting the containing amdgpu_cs from any IB (including non-main ones). Reviewed-by: Marek Olšák <[email protected]>
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