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* radeonsi: add radeonsi_zerovram driconfig optionTimothy Arceri2018-08-301-3/+7
| | | | | | | More and more games seem to require this so lets make it a config option. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0Marek Olšák2018-08-033-4/+58
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* radeonsi: use storage_samples instead of color_samples in most placesMarek Olšák2018-07-311-2/+1
| | | | | | | and use pipe_resource::nr_storage_samples instead of r600_texture::num_color_samples. Tested-by: Dieter Nützel <[email protected]>
* winsys/amdgpu: remove RADEON_SURF_FMASK leftoverMarek Olšák2018-07-191-7/+4
| | | | RADEON_SURF_FMASK is never set.
* winsys/amdgpu: fix VDPAU interop by having one amdgpu_winsys_bo per BO (v2)Marek Olšák2018-07-183-5/+41
| | | | | | | | | | | | Dependencies between rings are inserted correctly if a buffer is represented by only one unique amdgpu_winsys_bo instance. Use a hash table keyed by amdgpu_bo_handle to have exactly one amdgpu_winsys_bo per amdgpu_bo_handle. v2: return offset and stride properly Tested-by: Leo Liu <[email protected]> Acked-by: Leo Liu <[email protected]>
* winsys/amdgpu: use a better hash_pointer functionMarek Olšák2018-07-181-8/+5
| | | | | Tested-by: Leo Liu <[email protected]> Acked-by: Leo Liu <[email protected]>
* winsys/amdgpu: clean up error handling in amdgpu_bo_from_handleMarek Olšák2018-07-181-20/+16
| | | | | Tested-by: Leo Liu <[email protected]> Acked-by: Leo Liu <[email protected]>
* winsys/amdgpu: shorten bo->ws in amdgpu_bo_destroyMarek Olšák2018-07-181-9/+10
| | | | | Tested-by: Leo Liu <[email protected]> Acked-by: Leo Liu <[email protected]>
* winsys/amdgpu: clean up error handling in amdgpu_cs_submit_ibMarek Olšák2018-07-161-9/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: rework RADEON_PRIO flags to be <= 31Marek Olšák2018-07-162-5/+5
| | | | | | This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes. Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: use alloca when using global_bo_listMarek Olšák2018-07-161-9/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: remove label bo_list_errorMarek Olšák2018-07-161-12/+16
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: always update gfx_bo_list_counterMarek Olšák2018-07-161-3/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: make amdgpu_cs_context::flags & handles localMarek Olšák2018-07-162-22/+5
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* Shorten u_queue namesMarek Olšák2018-07-041-1/+1
| | | | | | | | There is a 15-character limit for thread names shared by the queue name and process name. Shorten the thread name to make space for the process name. Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: add a debug flag to zero vram allocationsGrazvydas Ignotas2018-06-213-0/+5
| | | | | | | | | | This allows to avoid having to see garbage in Dying Light loading screen at least, which probably expects Windows/NV behavior of all allocations being zeroed by default. Analogous to radv flag with the same name. Reviewed-by: Marek Olšák <[email protected]>
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-194-19/+19
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-301-5/+5
| | | | | | | | | | | | This just renames this as we want to add an shm handle which isn't really drm related. Originally by: Marc-André Lureau <[email protected]> (airlied: I used this sed script instead) This was generated with: git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g' Reviewed-by: Marek Olšák <[email protected]>
* amd: remove support for LLVM 4.0Marek Olšák2018-05-171-7/+0
| | | | | | | It doesn't support GFX9. Acked-by: Dave Airlie <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.Jan Vesely2018-05-101-1/+6
| | | | | | | | Fixes memory leak on module unload. CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/surface: add EQAA supportMarek Olšák2018-05-101-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't emit partial flushes for internal CS flushes onlyMarek Olšák2018-04-161-4/+8
| | | | | Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATEMarek Olšák2018-04-161-10/+26
| | | | | | | | There is a kernel patch that adds the new flag. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: don't set the display flag for obviously unsupported cases (v2)Marek Olšák2018-04-101-0/+1
| | | | | | | This enables the tile swizzle for some cases of the displayable micro mode, and it also fixes an addrlib assertion failure on Vega. Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: always allow GTT placements on APUsMarek Olšák2018-03-261-7/+5
| | | | Reviewed-by: Christian König <[email protected]>
* radeonsi: don't reallocate on DMABUF export if local BOs are disabledMarek Olšák2018-03-261-4/+3
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* ac/surface: compute tile swizzle for GFX9Marek Olšák2018-03-211-0/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
* winsys/amdgpu: pad compute IBsMarek Olšák2018-03-081-1/+3
| | | | | | v2: pad with PKT2 NOPs on SI Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-081-2/+3
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: request high addressesChristian König2018-02-281-4/+12
| | | | | | | | | We now have hopefully fixed all bugs regarding high addresses on Vega10 and Raven. Start to use the high range to make room for SVM in the low range. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu:add uvd hevc enc support in amdgpu csJames Zhu2018-02-211-0/+6
| | | | | | | Support UVD HEVC encode in amdgpu cs Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* winsys/amdgpu: enable 32-bit VM allocationsMarek Olšák2018-02-171-1/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: allow non page-aligned size bo creation from pointerMichal Navratil2018-02-061-4/+7
| | | | | | | | | Fix INVALID_OPERATION caused by BufferData with target EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD when the buffer size is not page aligned. Signed-off-by: Marek Olšák <[email protected]> Cc: 17.3 18.0 <[email protected]>
* winsys/amdgpu: add support for syncobj signaling v3Andres Rodriguez2018-01-302-1/+86
| | | | | | | | | | Add the ability to signal a syncobj when a cs completes execution. v2: corresponding changes for gallium fence->semaphore rename v3: s/semaphore/fence for pipe objects Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: set number of pb_cache buckets = number of heapsMarek Olšák2018-01-272-17/+12
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* pb_cache: let drivers choose the number of bucketsMarek Olšák2018-01-272-2/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: fix assertion failure with UVD and VCE ringsMarek Olšák2018-01-261-2/+1
| | | | Cc: 18.0 <[email protected]>
* radeonsi: Export signalled sync file instead of -1.Bas Nieuwenhuizen2018-01-261-0/+22
| | | | | | | | -1 is considered an error for EGL_ANDROID_native_fence_sync, so we need to actually create a sync file. Fixes: f536f45250 "radeonsi: implement sync_file import/export" Reviewed-by: Dave Airlie <[email protected]>
* autotools: include meson build files in tarballDylan Baker2018-01-191-0/+2
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* winsys/amdgpu: disable local BOs again due to worse performanceMarek Olšák2017-12-111-2/+3
| | | | | Cc: 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: make IBs use read-only memoryMarek Olšák2017-12-061-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: always place sparse buffers in VRAMNicolai Hähnle2017-12-061-2/+3
| | | | | | | | | | | | Together with "radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check", this ensures that sparse buffers are placed in VRAM. Noticed by an assertion that started triggering with commit d4fac1e1d7 ("gallium/radeon: enable suballocations for VRAM with no CPU access") Fixes KHR-GL45.sparse_buffer_tests.BufferStorageTest in debug builds. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* winsys/amdgpu: add RADEON_FLAG_READ_ONLYMarek Olšák2017-12-051-1/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move setting VRAM|GTT into winsysesMarek Olšák2017-12-051-1/+13
| | | | | | The combined VRAM|GTT heap will be removed. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: remove always-true BRAHMA_BUILD defineEric Engestrom2017-12-011-3/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*Marek Olšák2017-11-292-3/+3
| | | | | | and handle PIPE_FLUSH_HINT_FINISH in r300. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: add vcn enc cs supportBoyuan Zhang2017-11-171-1/+6
| | | | | | | New cs support is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-131-1/+0
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fencesNicolai Hähnle2017-11-092-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to fix the following interleaving of operations that can arise from deferred fences: Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = deferred flush <------- application-side synchronization -------> fence_server_sync(f) ... flush() flush() We will now stall in fence_server_sync until the flush of context 1 has completed. This scenario was unlikely to occur previously, because applications seem to be doing Thread 1 / Context 1 Thread 2 / Context 2 -------------------- -------------------- f = glFenceSync() glFlush() <------- application-side synchronization -------> glWaitSync(f) ... and indeed they probably *have* to use this ordering to avoid deadlocks in the GLX model, where all GL operations conceptually go through a single connection to the X server. However, it's less clear whether applications have to do this with other WSI (i.e. EGL). Besides, even this sequence of GL commands can be translated into the Gallium-level sequence outlined above when Gallium threading and asynchronous flushes are used. So it makes sense to be more robust. As a side effect, we no longer busy-wait on submission_in_progress. We won't enable asynchronous flushes on radeon, but add a cs_add_fence_dependency stub anyway to document the potential issue. Reviewed-by: Marek Olšák <[email protected]>
* util: move os_time.[ch] to src/utilNicolai Hähnle2017-11-092-2/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
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